MPW PLANNING
MPW Shuttle Schedule & Foundry Coverage
Compare published MPW calendars from 4 foundries: UMC, X-FAB, GlobalFoundries and IHP. Dated calendars are separate from indicative monthly cadence. Ask TOMPW to confirm the current run, GDS cut-off and seat availability for your target process before committing a design to a shuttle.
Common MPW use cases
- ✓First silicon for a new ASIC or SoC
- ✓Architecture and IP validation
- ✓Early customer sampling
- ✓Low-volume or research designs
Instead of launching a dedicated wafer, designs are grouped into scheduled shuttle runs. Missing a tape-out deadline usually means waiting for the next shuttle, which can delay silicon by weeks or months.
PUBLISHED FOUNDRY CALENDARS
Real shuttle dates, as published by the foundries
These tables are transcribed from the foundries' own shuttle pages: processes run down the left, months run across the top. Where a foundry publishes a day-level tape-in date, the day is shown; where it publishes only a launch month, the month is marked. Every table links back to its source and carries the date it was last checked.
UMC
UMC — 2026 Silicon Shuttle plan
| 2026 | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Process / platform | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec | Windows |
| 22nm (22ULR / 22ULP / 22ULL logic & mixed-mode) | Jan | – | Mar | Apr | – | Jun | Jul | – | Sep | Oct | – | Dec | Jan · Mar · Apr · Jun · Jul · Sep · Oct · Dec |
| 28nm (28HPC / 28HPC+ logic & mixed-mode) | – | Feb | – | – | May | – | – | Aug | – | – | Nov | – | Feb · May · Aug · Nov |
| 40nm (40LP / 40G / 40ULP logic & mixed-mode) | – | – | Mar | Apr | – | Jun | – | Aug | – | Oct | Nov | Dec | Mar · Apr · Jun · Aug · Oct · Nov · Dec |
| 55nm / 65nm (logic, mixed-mode, RF — LL) | Jan | Feb | – | Apr | – | Jun | Jul | – | – | Oct | – | – | Jan · Feb · Apr · Jun · Jul · Oct |
| 0.11µm logic / mixed-mode / RF (Al BEOL) | – | Feb | – | – | May | – | Jul | – | Sep | – | – | Dec | Feb · May · Jul · Sep · Dec |
| 0.11 / 0.13 / 0.15 / 0.162µm logic & mixed-mode (Cu BEOL) | Jan | – | – | – | – | – | – | Aug | – | – | – | – | Jan · Aug |
| 0.18µm logic GII, mixed-mode / RF | – | – | – | Apr | – | – | – | – | – | Oct | – | – | Apr · Oct |
What a marked cell means: A marked month indicates a regular shuttle launch, if the minimum number of paid seats has been filled.
Registration rule: UMC asks customers to contact their sales representative for shuttle details; the most current schedule is on MyUMC.
- UMC publishes months, not day-level tape-out dates. Treat a marked month as the launch month and confirm the GDS cut-off for the specific run.
- A marked month indicates a regular shuttle launch only if the minimum number of paid seats has been filled. Otherwise UMC reserves the right to make adjustments.
X-FAB
X-FAB — MPW Schedule 2026
| 2026 | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Process / platform | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec | Windows |
| XT011 — 110nm CMOS | – | – | 9 Marout 24 Aug 2026 | – | – | 8 Junout 23 Nov 2026 | – | 24 Augout 8 Feb 2027 | – | – | 16 Novout 3 May 2027 | – | 9 Mar · 8 Jun · 24 Aug · 16 Nov |
| XR013 — 130nm RF SOI | – | – | – | 10 Aprout 8 Sep 2026 | – | – | – | – | – | 30 Octout 16 Mar 2027 | – | – | 10 Apr · 30 Oct |
| XH018 — 180nm HV CMOS / eFlash | 19 Janout 6 Jul 2026 | – | – | 6 Aprout 21 Sep 2026 | – | 29 Junout 14 Dec 2026 | – | – | – | 12 Octout 29 Mar 2027 | – | – | 19 Jan · 6 Apr · 29 Jun · 12 Oct |
| XP018 — 180nm CMOS | – | 9 Febout 20 Jul 2026 | – | – | – | 8 Junout 16 Nov 2026 | – | – | 14 Sepout 22 Feb 2027 | – | – | – | 9 Feb · 8 Jun · 14 Sep |
| XT018 — 180nm BCD-on-SOI | 8 Janout 13 Aug 2026 | – | 16 Marout 19 Oct 2026 | – | 4 Mayout 7 Dec 2026 | – | – | 3 Augout 8 Mar 2027 | – | – | 16 Novout 21 Jun 2027 | – | 8 Jan · 16 Mar · 4 May · 3 Aug · 16 Nov |
| XS018 — 180nm CMOS | – | 23 Febout 27 Jul 2026 | – | – | – | – | 13 Julout 14 Dec 2026 | – | – | – | – | – | 23 Feb · 13 Jul |
| XH035 — 350nm HV CMOS | – | – | 6 Marout 24 Jul 2026 | – | – | – | – | 7 Augout 25 Dec 2026 | – | – | 6 Novout 26 Mar 2027 | – | 6 Mar · 7 Aug · 6 Nov |
| XG035 — GaN | – | – | – | 3 Aprout 24 Jul 2026 | – | – | 17 Julout 6 Nov 2026 | – | – | – | 27 Novout 19 Mar 2027 | – | 3 Apr · 17 Jul · 27 Nov |
| XPH90 — 90nm silicon photonics | – | – | – | – | 8 Mayout 20 Nov 2026 | – | – | – | 4 Sepout 19 Mar 2027 | – | 20 Novout 4 Jun 2027 | – | 8 May · 4 Sep · 20 Nov |
What a marked cell means: The date is the published tape-in (tape-out) date. The second line is the published samples-out date for that run.
Registration rule: Registration must be completed at least two weeks before the tape-in date. The DRC-clean released database plus documentation must be submitted by the data-release date.
- Samples-out dates assume the most complex process variant is used; by that date dice in wafflepack can be delivered.
- X-FAB states that all changes to the schedule are updated on that page only, so the source link is the authoritative version.
- If no listed run fits, X-FAB asks customers to contact their local sales manager about additional MPW runs available on request.
GlobalFoundries
GlobalFoundries — GlobalShuttle MPW schedule
| 2026 | 2027 | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Process / platform | Sep | Oct | Nov | Dec | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec | Windows |
| 22nm FDSOI (22FDX) | Sep | Oct | Nov | Dec | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | – | Oct | Nov | – | Sep · Oct · Nov · Dec · Jan · Feb · Mar · Apr · May · Jun · Jul · Aug · Oct · Nov |
| 12nm LP+ | – | – | Nov | – | – | Feb | – | – | May | – | – | Aug | – | – | Nov | – | Nov · Feb · May · Aug · Nov |
| 28nm SLP | – | – | Nov | – | – | – | Mar | – | – | – | – | – | Sep | – | – | – | Nov · Mar · Sep |
| 40nm | Sep | – | – | Dec | – | – | Mar | – | – | Jun | – | – | Sep | – | – | Dec | Sep · Dec · Mar · Jun · Sep · Dec |
| 55nm BCDlite | – | – | Nov | – | – | Feb | – | – | May | – | – | Aug | – | – | Nov | – | Nov · Feb · May · Aug · Nov |
| 110 / 130nm | – | – | Nov | – | – | Feb | – | – | May | – | – | Aug | – | – | Nov | – | Nov · Feb · May · Aug · Nov |
| 130nm | – | – | Nov | – | – | Feb | – | – | May | – | – | Aug | – | – | Nov | – | Nov · Feb · May · Aug · Nov |
| 150nm | – | – | – | – | – | – | – | – | – | Jun | – | – | – | – | – | – | Jun |
| 180nm | Sep | – | – | – | Jan | – | – | – | May | – | – | Aug | – | – | Nov | – | Sep · Jan · May · Aug · Nov |
| 45SPCLO (silicon photonics) | – | Oct | – | – | – | Feb | – | – | May | – | – | Aug | – | – | Nov | – | Oct · Feb · May · Aug · Nov |
| 45RFSOI | Sep | – | – | – | – | – | Mar | – | – | – | – | – | Sep | – | – | – | Sep · Mar · Sep |
| 45RFE | – | – | Nov | – | – | – | – | – | May | – | – | – | – | – | Nov | – | Nov · May · Nov |
| 9HP (SiGe BiCMOS) | Sep | – | – | – | – | – | – | – | May | – | – | – | – | – | Nov | – | Sep · May · Nov |
| 8XP (SiGe) | – | – | Nov | – | – | – | – | – | May | – | – | – | – | – | Nov | – | Nov · May · Nov |
| RFGaN-LV1 (90RFGaN) | – | – | – | Dec | – | – | – | Apr | – | – | Jul | – | – | Oct | – | – | Dec · Apr · Jul · Oct |
| RFGaN1 (130RFGaN) | – | Oct | – | – | – | – | – | – | May | – | – | – | – | – | Nov | – | Oct · May · Nov |
| CBIC | – | – | Nov | – | – | – | – | – | May | – | – | – | – | – | Nov | – | Nov · May · Nov |
| SLATE wafer-to-wafer bonding with 9SW | – | – | Nov | – | – | – | – | – | – | – | – | – | – | – | – | – | Nov |
| AMF MPW | Sep | – | Nov | – | – | – | – | – | – | – | – | – | – | – | – | – | Sep · Nov |
What a marked cell means: A marked month denotes the shuttle tape-out month, once minimum demand is fulfilled.
Registration rule: AMF shuttle runs require GDS by the 15th of the previous month to secure a slot, with a maximum of three DRC iterations.
- A marked month denotes the shuttle tape-out month once minimum demand is fulfilled. GF reserves the right to modify the plan.
- GF customers can see the current schedule on GF Connect; new customers are asked to contact GF directly.
- AMF runs are marked separately: submit GDS by the 15th of the previous month, with a maximum of three DRC iterations.
IHP
IHP — MPW schedule and price list, 2026
| 2026 | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Process / platform | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec | Windows |
| SG13CMOS & SG13CMOS5L (RF CMOS, incl. open-source runs) | – | – | 30 Mar | – | – | – | 13 Jul | – | – | – | 9 Nov | – | 30 Mar · 13 Jul · 9 Nov |
| SG13S (0.13µm SiGe BiCMOS) | – | – | – | – | – | 1 Jun | – | 23 Aug | – | – | – | 7 Dec | 1 Jun · 23 Aug · 7 Dec |
| SG13G2 (0.13µm SiGe BiCMOS, fT/fmax 350/450 GHz) | – | – | – | – | – | 1 Jun | – | 23 Aug | – | – | – | 7 Dec | 1 Jun · 23 Aug · 7 Dec |
| SG13G3 | – | – | – | – | – | – | – | 23 Aug | – | – | – | 7 Dec | 23 Aug · 7 Dec |
| SG13SCu (Cu BEOL option) | – | – | 16 Mar | – | – | – | – | 23 Aug | – | – | – | 7 Dec | 16 Mar · 23 Aug · 7 Dec |
| SG13G2Cu (Cu BEOL option) | – | – | – | – | – | – | – | 23 Aug | 29 Sep | – | – | 7 Dec | 23 Aug · 29 Sep · 7 Dec |
| SG13G3Cu (Cu BEOL option) | – | – | 16 Mar | – | – | – | – | 23 Aug | – | – | – | 7 Dec | 16 Mar · 23 Aug · 7 Dec |
| SG25H7_EPIC (photonic BiCMOS) | – | – | – | – | – | – | – | – | – | – | 2 Nov | – | 2 Nov |
| MEMRES (RRAM module on SG13G2) | – | – | – | – | – | 1 Jun | – | – | – | – | – | 7 Dec | 1 Jun · 7 Dec |
What a marked cell means: The date is the published tape-in date. Each tape-in row also carries a planned shipment date per technology on the source page.
Registration rule: Runs with lower priority, and any run requiring a minimum area, need registration four weeks before tape-out plus foundry confirmation.
- IHP marks some runs as lower priority; those carry a minimum-area requirement and need registration four weeks before tape-out plus foundry confirmation.
- Minimum area on selected runs starts at about 0.8 mm². Combining 0.25µm-based and 0.13µm-based runs on one wafer is not possible.
- IHP also publishes a 2027 schedule, and states that changes to it are possible until 1 December 2026.
NO PUBLIC CALENDAR
Foundries that share dates on request
Several major programmes do not publish a dated grid at all — the schedule is released to customers through the foundry portal or through its access partners. For these, the current window is confirmed per project rather than scraped from a page.
TSMC
Profile →Shuttle dates are released to customers through the TSMC shuttle programme and its design-centre partners rather than published openly, so the live window is confirmed per project.
SMIC
Profile →MPW windows are communicated through the foundry and its regional channel; no dated public calendar is published.
Samsung Foundry
Profile →Prototype runs are reserved through the B2B CONNECT system and regional partners; schedules are visible inside that system rather than on a public page.
ams OSRAM
Profile →The 2026 MPW programme is published with its process options — new 180nm mixed-signal CMOS and 180nm BCD (1.8/3.3 V, 1.8/5 V, 1.8/5 V/70 V), plus 350nm CMOS, HV and embedded-flash — with samples typically about 10–12 weeks after tape-out. The dated calendar sits on the Full-Service Foundry pages and with its access partners (CIME-P, Fraunhofer IIS, MEDS Technologies).
Tower Semiconductor
Profile →Shuttle schedules and the available process options are confirmed through the foundry for each project; this page does not provide a dated public booking calendar.
DB Hitek (Dongbu)
Profile →Runs are arranged through the foundry; no public dated calendar.
FOUNDRY COVERAGE
MPW nodes by foundry
Each foundry runs its own shuttle program at its own set of nodes. The list below reflects MPW coverage across the foundries TOMPW coordinates; click through for the full profile and TOMPW support scope.
TSMC
Profile →Broadest advanced-node MPW through the TSMC shuttle program; advanced-node windows are evaluated case by case.
UMC
Profile →Strong mixed-signal, RF, HV, BCD and eFlash MPW platforms for IoT, display driver and power applications. Windows below show the monthly rhythm TOMPW tracks for UMC; a run launches once it fills, and we confirm the live window per project.
GlobalFoundries
Profile →Differentiated specialty portfolio; 22FDX FD-SOI is a unique low-power MPW differentiator.
SMIC
Profile →Deep mature-to-mainstream MPW coverage with competitive cost for Asia-based supply chains.
Tower
Profile →Specialty foundry focused on analog, RF, photonics and MEMS MPW platforms.
IHP
Profile →Premier SiGe BiCMOS and photonics research foundry; MPW shuttles for RF, mmWave and optical engines.
X-FAB
Profile →Specialty analog and mixed-signal foundry with strong HV, SOI and MEMS MPW platforms.
DB Hitek (Dongbu)
Profile →Specialty analog, BCD and mixed-signal foundry (operates as Dongbu Electronics) for power and sensor applications.
Samsung Foundry
Profile →Broad node roadmap from 130nm to 3nm GAA; MPW runs through the B2B CONNECT reservation system with secure, isolated prototype flows.
ams OSRAM
Profile →Analog and mixed-signal MPW platforms. Process options, the access route and current shuttle dates require project confirmation.
VIS (Vanguard)
Profile →Taiwan specialty foundry strong in power, analog and display-driver platforms across mature nodes.
PSMC (Powerchip)
Profile →Taiwan foundry with broad mature-to-mainstream coverage and specialty logic/mixed-signal platforms.
SilTerra
Profile →Malaysia pure-play foundry with regular CMOS, MEMS and RF MPW programs across mature nodes.
WIN Semiconductors
Profile →World's largest pure-play compound-semiconductor foundry; regular GaAs/GaN MPW shuttles for RF and mmWave applications.
CanSemi
Profile →China-based foundry for analog, mixed-signal, PMIC and CIS platforms from 180nm to 40nm.
CSMC
Profile →China-based foundry with deep mature-node BCD, CMOS and HV analog coverage for power and industrial designs.
SJ SEMI
Profile →China specialty foundry for BCD, HV and automotive-grade power/analog platforms.
HLMC
Profile →China-based foundry for mainstream logic and specialty nodes from 28nm to 90nm.
Sanan
Profile →China's leading compound-semiconductor foundry for RF, power and photonic devices (platform-based, not standard CMOS MPW).
XMC
Profile →China specialty foundry focused on NOR Flash, CMOS image sensors and MEMS/analog across mature nodes.
Silex Microsystems
Profile →World-leading pure-play MEMS foundry in Sweden (part of Sai MicroElectronics); process- and design-based engagements.
AWSC
Profile →Taiwan pure-play GaAs foundry for RF/microwave; pHEMT and HBT platforms for PA, WiFi/5G and optical devices.
Dynax
Profile →China-based GaN RF foundry; wafer foundry on 0.45–0.1 µm GaN HEMT for comms, radar and RF energy.
STMicroelectronics
Profile →European IDM with premium-foundry model; BCD, SiGe BiCMOS, FD-SOI, RF-SOI, MEMS, SiC and GaN specialty technologies.
NSI (SMIC Ningbo)
Profile →China specialty foundry (SMIC Ningbo) on 200 mm lines; RF front-end, MEMS and high-voltage analog, incl. BAW (SASFR) filters.
SK Key Foundry
Profile →Korea-based 200mm specialty foundry (ex-MagnaChip, SK Group) with analog/mixed-signal, power BCD, eNVM and SiC MOSFET platforms; runs an MPW shuttle program.
Sai Micro
Profile →China-based pure-play MEMS foundry (Beijing 8-inch line + Silex Sweden); sensors, BAW, optical MEMS and micro-fluidics. Process- and design-based engagements.
INDICATIVE CADENCE
Indicative month rhythm for other platforms
The grids above are the published calendars. This one is different: it marks, by month, whether a node commonly has a window across 8 foundries and 56 MPW platforms, based on observed cadence rather than a published dated schedule. Use it to sense how often a node generally runs — then treat the confirmed run as the real date.
GlobalFoundries
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SiGe 8XP | ● | ● | ● | ● | ||||||||
| 130nm BCDlite – Gen2 | ● | ● | ||||||||||
| 55 nm BCDlite | ● | ● | ● | ● | ||||||||
| 45RFE | ● | ● | ||||||||||
| 45nm SPCLO – Silicon Photonics | ● | ● | ● | |||||||||
| 28 nm SLPe | ● | ● | ● | |||||||||
| 22 nm FDSOI | ● | ● | ● | ● | ● | ● | ● | |||||
| 12 nm LP+ | ● | ● |
IHP
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SG13C SiGe:C RF CMOS | ● | ● | ● | |||||||||
| SG13G2 SiGe:C Bipolar/Analog | ● | ● | ● | |||||||||
| SG13G2Cu (FEOL process SG13G2 + Cu BEOL option from X-FAB) | ● | ● | ● | |||||||||
| SG13G3Cu (FEOL process + Cu BEOL option from X-FAB) | ● | ● | ||||||||||
| SG13G3 (FEOL process SG13G3Cu + Al-BEOL option)* | ● | ● | ||||||||||
| SG13S SiGe:C Bipolar/Analog | ● | ● | ● | |||||||||
| SG13SCu (FEOL process SG13S + Cu BEOL option from X-FAB) | ● | ● | ● | |||||||||
| MEMRES for SG13S | ● | ● | ||||||||||
| SG25 PIC (Photonics, Ge Photo-diode, BEOL) | ● | |||||||||||
| SG25H5_EPIC high performance BiCMOS + Photonic | ● | |||||||||||
| BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV or RDL | ● |
TSMC
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0.13µm CMOS BCD plus (12-inch) | ● | ● | ● | ● | ||||||||
| 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch) | ● | ● | ● | ● | ||||||||
| 90nm CMOS Logic or MS/RF, GP or LP | ● | ● | ● | ● | ||||||||
| 65nm CMOS Logic or MS/RF, GP or LP | ● | ● | ● | ● | ● | ● | ||||||
| 40nm CMOS Logic or MS/RF, LP (no triple gate oxide) | ● | ● | ● | ● | ● | ● | ● | ● | ● | |||
| 40nm CMOS Logic or MS/RF, GP (no triple gate oxide) | ● | ● | ● | ● | ||||||||
| 28nm CMOS Logic or RF HPC/HPC+ | ● | ● | ● | ● | ● | ● | ● | |||||
| 22nm CMOS Logic or RF ULL | ● | ● | ● | ● | ● | ● | ||||||
| 16nm CMOS Logic or RF FinFET Compact | ● | ● | ● | ● | ● | ● | ||||||
| 7nm CMOS Logic FinFET | ● | ● | ● |
UMC
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 22nm Logic / Mixed-Mode (22ULR) | ● | ● | ● | ● | ● | ● | ● | ● | ||||
| 28N Logic/Mixed-Mode – HPC | ● | ● | ● | ● | ||||||||
| 40N Logic/Mixed-Mode – LP | ● | ● | ● | ● | ● | ● | ● | |||||
| 55N / 65N Logic/Mixed-Mode/RF – LL | ● | ● | ● | ● | ● | ● | ||||||
| L110AE 0.11µm Logic/Mixed-Mode/RF (Al BEOL) | ● | ● | ● | ● | ● | |||||||
| 0.11 / 0.13 / 0.15 / 0.162µm Logic/Mixed-Mode (Cu BEOL) | ● | ● | ||||||||||
| L180 0.18µm Logic GII, Mixed-Mode/RF | ● | ● |
X-FAB
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| T011 0.11µ HV SOI CMOS | ● | ● | ● | ● | ||||||||
| R013 0.13µ RF SOI CMOS * | ● | ● | ||||||||||
| R013 0.13µ XIPD | ● | ● | ||||||||||
| H018 0.18µ HV NVM CMOS E-FLASH | ● | ● | ● | ● | ||||||||
| P018 0.18µ NVM CMOS * | ● | ● | ● | |||||||||
| T018 0.18µ HV SOI CMOS | ● | ● | ● | ● | ||||||||
| S018 0.18µ OPTO * | ● | ● | ||||||||||
| H035 0.35µ HV CMOS | ● | ● | ● | |||||||||
| MB10 MEMS | ● |
DB Hitek (Dongbu)
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Analog /BCD (AN07/AN180/HP180 BD180LV/BD180MV/ BD180XH/BD180XA) 0.18µm | ● | ● | ● | ● | ● | ● | ● | ● | ● | ● | ● | ● |
| Analog/BCD (BEOL 0.15um BD18LVA/AN180 Gen2) 0.15µm | ● | ● | ● | ● | ● | ● | ||||||
| BCD (BD180XA) 0.18µm | ● | ● | ||||||||||
| Analog/BCD SOI (BD130/RS13) 0.13µm | ● | ● | ● | ● | ||||||||
| Mixed Signal/RF HRS 0.11µm | ● | ● | ● | ● |
Samsung Foundry
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 28nm (28LPP) | ● | |||||||||||
| 65nm (LF6/LF6S) | ● | ● | ||||||||||
| 130nm (BCD) | ● | ● | ● |
WIN Semiconductors
Profile →| Process / Node | Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| NP12-1B (GaAs) | ● | ● | ● | ● | ||||||||
| PIN1-11 (GaAs) | ● | |||||||||||
| PP10-29 (GaN) | ● |
Blank cells mean no public month-level reference is recorded for that node in that month. Windows reflect publicly documented MPW cadence and are confirmed per project — tell us your target foundry and node and we will lock the live run.
SHUTTLE CADENCE
Typical MPW frequency by node band
Cadence is not uniform. It follows a monthly or quarterly rhythm that depends on foundry, technology node, process maturity and demand. Use the table below as a planning reference rather than a guarantee of a specific date.
| Node band | Typical MPW frequency | Planning note |
|---|---|---|
| Mature (≥180nm) | Monthly to quarterly | Frequent windows; often the easiest to align with a program timeline. |
| 130nm – 65nm | Monthly to quarterly | Broad fab availability across multiple qualified platforms. |
| 40nm – 28nm | Quarterly, multiple windows/year | Popular nodes run several shuttles per year at major fabs. |
| 22nm – 14nm (FinFET/FF) | 2–4× per year | Less frequent, more structured calendars; qualification often required. |
| ≤7nm advanced | 2–4× per year | Fixed calendars with higher minimum participation and lead-time planning. |
VISUAL SUMMARY
Shuttle density at a glance
The same cadence data from the tables above, drawn as a yearly rhythm. Mature-node programs can usually find a window every month, while advanced-node teams plan around a few fixed slots.
Swipe horizontally to read the full chart.
PRICING LOGIC
What a shuttle seat costs, in industry ranges
MPW pricing is not fixed. It depends on the specific run you target, so the useful number is the price for an exact shuttle at your chosen foundry and node. These are wide industry reference ranges for orientation only.
| MPW seat — mature node (≥180nm) | US$3,000 – $30,000 |
| MPW seat — 130nm to 55nm | US$8,000 – $80,000 |
| MPW seat — 40nm to 28nm | US$25,000 – $200,000 |
| MPW seat — 22nm and below | US$50,000 – $400,000 |
These are industry reference ranges, not a quotation and not an offer.
- Every band on this page is deliberately wide. It is published so you can sanity-check whether a programme is realistic before you write to anyone — not so you can budget against it.
- Actual pricing moves with the season and with capacity. Foundry and OSAT utilisation changes month to month, and a window that is cheap in a soft quarter can be materially more expensive in a tight one.
- Mask, substrate, leadframe, gold, copper and tester-time costs all move independently of the node you chose.
NEXT MOVE
Request the live schedule and pricing
Tell us your target foundry, process node, approximate die size and preferred shuttle window. You do not need a finalized GDS to start the conversation — a lightweight brief is enough to confirm availability and pricing for the relevant run.
FAQ
Questions about MPW scheduling
A multi-project wafer run where several customer designs share one mask set. Each participant pays for a portion of the wafer instead of a dedicated reticle, which dramatically lowers mask and fabrication cost for prototype and low-volume silicon.
Cadence depends on foundry, process node, process maturity and demand. Mature nodes commonly run monthly or quarterly, while advanced nodes typically offer two to four windows per year. Missing a tape-out deadline usually means waiting for the next shuttle.
Yes, for the published calendars section. Those grids are transcribed from the foundries' own shuttle pages — UMC, X-FAB, GlobalFoundries and IHP — with the source linked and the check date shown on each table. X-FAB and IHP publish day-level tape-in dates; UMC and GlobalFoundries publish launch months. The section further down, labelled indicative cadence, is different: it reflects observed month-level rhythm rather than a published dated schedule.
For the published calendars, a marked cell is the launch or tape-in month the foundry has published, and it launches only once minimum demand or minimum paid seats are reached — both UMC and GlobalFoundries state this explicitly. For the indicative section, a mark means the node commonly has a window that month based on observed cadence. Either way it is a planning reference: exact registration cut-off and GDS submission deadlines shift with demand and capacity, so the live run is confirmed per project.
As a wide industry reference: roughly US$3,000–$30,000 for a mature-node seat, US$8,000–$80,000 from 130nm to 55nm, US$25,000–$200,000 from 40nm to 28nm, and US$50,000–$400,000 at 22nm and below. These are reference ranges, not quotations — they move with season, capacity, currency, die size and block count. See the full cost range page for the complete list and the disclaimer.
Yes. Many teams validate first silicon through MPW or NTO, then move into full mask once the design and commercial outlook are clearer. Planning that transition early avoids a costly process port later.
CALCULATORS
Estimate cost and dies with free calculators
Tapeout / Calculator
Die Per Wafer Calculator
Count complete dies from Shot/Field layouts with flat or notched wafer boundaries, edge clearance and optional yield estimates.
Open toolTapeout / Calculator
MPW Cost Sharing Calculator
Allocate an agreed MPW shared cost by booked block area and block count, without predicting delivered dies.
Open toolTapeout / Calculator
Wafer & Unit Cost Calculator
Turn a wafer run into a per-chip cost: dies per wafer, yield, packaging and test, plus a target margin.
Open toolTapeout / Calculator
Node / Wafer DPW Comparison
Compare dies per wafer and cost per die across 100/150/200/300 mm wafers for a fixed die.
Open toolTapeout / Calculator
Tape-out Budget Estimator
Full program model: DPW, yield, packaging, HBM, test, NRE and volume → unit cost, price and gross margin.
Open toolPackaging / Calculator
Package Selection Advisor
Match QFN, BGA, WLCSP, Flip-Chip, SiP or legacy leaded packages to your IO, power, RF, cost and form-factor constraints.
Open toolTesting / Calculator
Test Cost & Yield Calculator
Estimate ATE test cost per device and per good unit from tester rate, test time, handler cost, volume and test yield.
Open toolDesign / Calculator
IP Cost & Licensing Estimator
Model IP licence fees, per-die royalties, support and integration effort across program volume — with the buy-vs-build break-even point.
Open tool