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TSMCFoundry profile · process nodes · MPW shuttle windows · tape-out access

TSMC is the world's largest dedicated semiconductor foundry, serving leading fabless semiconductor companies. TOMPW Service supports MPW shuttle access, NTO coordination and production mask programs with TSMC across multiple nodes.

Reviewed October 29, 202613 process nodes listed: 3nm, 5nm, 7nm and moreScope: MPW, NTO and production evaluation
TSMC — representative silicon and device imagery from programs we support

Representative imagery from semiconductor programs we have supported or analysed

Process Nodes

3nm5nm7nm12nm16nm22nm22ULP22ULL28nm40nm65nm90nmMature nodes

Technologies & Platforms

CMOS
BCD
RF CMOS
SOI
SiGe BiCMOS

TOMPW Support Capabilities

✓MPW shuttle windows
✓NTO / engineering run support
✓Full mask production
✓Advanced node tape-out coordination
✓Package and test alignment

Best For

AI and HPC programsMobile and consumer SoCAdvanced node first-silicon validationTeams needing mature advanced-node support

Notes

  • Advanced node programs are evaluated case by case based on schedule and commercial model.
  • TOMPW helps coordinate MPW to production transition on TSMC nodes.

Plan the manufacturing route

Compare the process requirements with the package and test path before selecting a manufacturing route. Confirm the PDK, supplier acceptance, commercial terms and delivery scope in the project proposal.

Discuss TSMC for Your Program

Share the application, process requirements and target quantities. TOMPW will review feasibility and identify the access, package and test conditions to confirm for TSMC.

Email for a Quote

COMMON QUESTIONS

Planning a TSMC project

Can TOMPW arrange MPW or shuttle runs at TSMC?

TOMPW reviews MPW, NTO and full-mask options for TSMC projects. Process acceptance, PDK access, run availability, quantities and delivery dates are confirmed for the specific project before booking.

What support does TOMPW provide beyond the wafer at TSMC?

TOMPW can scope packaging, final test, PCB and assembly work alongside the wafer requirements. The package route, responsible suppliers, test coverage and acceptance criteria are agreed in the project proposal.

How do I get a quote for a TSMC engagement?

Email market@tompwservice.com with the application, target process, program stage, volume and package or test needs. Start with non-confidential requirements; design files can follow through an agreed secure handoff.

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RELATED SERVICES

Services that pair with a TSMC engagement

MPW / SHUTTLE ACCESS

Plan a TSMC MPW by process node

TOMPW coordinates multi-project wafer runs at TSMC across the nodes below. Open a node to see typical applications, what the run involves and how to book a shuttle slot.

MPW SHUTTLE PLAN

Shuttle windows at TSMC by process node

The months below mark where a window commonly opens on each platform. A run launches once it fills, so read this as planning rhythm rather than a bookable date — send TOMPW your node and target quarter and we will tell you which run you can actually join.

0.13µm CMOS BCD plus (12-inch)

janfebmaraprmayjunjulaugsepoctnovdec

0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)

janfebmaraprmayjunjulaugsepoctnovdec

90nm CMOS Logic or MS/RF, GP or LP

janfebmaraprmayjunjulaugsepoctnovdec

65nm CMOS Logic or MS/RF, GP or LP

janfebmaraprmayjunjulaugsepoctnovdec

40nm CMOS Logic or MS/RF, LP (no triple gate oxide)

janfebmaraprmayjunjulaugsepoctnovdec

40nm CMOS Logic or MS/RF, GP (no triple gate oxide)

janfebmaraprmayjunjulaugsepoctnovdec

28nm CMOS Logic or RF HPC/HPC+

janfebmaraprmayjunjulaugsepoctnovdec

22nm CMOS Logic or RF ULL

janfebmaraprmayjunjulaugsepoctnovdec

16nm CMOS Logic or RF FinFET Compact

janfebmaraprmayjunjulaugsepoctnovdec

7nm CMOS Logic FinFET

janfebmaraprmayjunjulaugsepoctnovdec