ARCHITECTURE TO RTL
Design Support from Specification to Tape-Out Readiness
TOMPW supports customers who need a partner to bridge product intent, design implementation and the manufacturing path that follows.
Included Scope
What this service is built to handle
- Architecture and requirement alignment
- RTL development and IP integration planning
- Low-power and implementation-oriented design thinking
- Cross-team coordination with verification and physical design stages
Best Fit
Common situations where this path makes sense
- Teams building a first custom chip product
- Customers lacking full internal ASIC staffing
- Programs needing design and manufacturing handoff continuity
Deliverables
Typical outputs from TOMPW coordination
- Design scope definition
- RTL and integration support
- Handoff package for verification and backend teams
- Execution coordination with downstream tape-out flow
ENGAGEMENT MODEL
How ASIC / SoC Design runs stage by stage
Design support starts wherever the programme currently sits. Some teams arrive with a specification and nothing else, others arrive with RTL that has never been through a manufacturing review.
Stage 1
Specification review
What we need from you
- • Target application and performance envelope
- • Power, area and cost boundaries
- • IP that is already owned or licensed
What TOMPW handles
- • Architecture assumptions made explicit
- • Node and package candidates that fit the envelope
- • Risk list for the parts that drive schedule
Exit gate: Specification is stable enough to plan implementation.
Stage 2
Implementation planning
What we need from you
- • Block-level ownership inside the buyer's team
- • EDA tool chain and flow preference
- • Verification expectations
What TOMPW handles
- • RTL and integration work breakdown
- • Interface definition between blocks
- • Review cadence and checkpoint list
Exit gate: Block interfaces frozen.
Stage 3
Pre-tape-out readiness
What we need from you
- • Final netlist or RTL freeze
- • Design constraints for the target process
- • Sign-off requirements from the chosen foundry
What TOMPW handles
- • Readiness gap list against the foundry checklist
- • Handoff package for physical design or tape-out
- • Open issue register carried into the next stage
Exit gate: Design acknowledged as ready by the downstream team.
TOMPW does not replace a full design house. The role is to keep product intent, implementation choices and the manufacturing path pointing the same way.
Limits worth agreeing before you commit
- • Design results depend on the quality of the starting specification; TOMPW flags gaps rather than absorbing them silently.
- • Tool licences usually remain with the customer or their chosen design house.
- • Block-level PPA numbers are estimates until the design is run through the target process kit.
RESPONSIBILITY MATRIX
Who does the work, and who answers for it
Responsible does the work. Accountable is the single party who answers for the outcome — one per row, always. Consulted is asked before the decision; Informed is told after it.
| Item | Responsible | Accountable | Consulted | Informed |
|---|---|---|---|---|
| Product specification and acceptance criteria | You | You | TOMPW | Design partner |
| Process and foundry selection | TOMPW | You | Foundry | OSAT |
| PDK access, NDA and export-control screening | TOMPW | Foundry | You | Design partner |
| RTL / netlist delivery and freeze | You | You | TOMPW | Design partner |
| Physical design execution and timing sign-off | Design partner | TOMPW | You | Foundry |
| Mask set and NRE purchase | You | You | TOMPW | Foundry |
| Wafer starts, capacity slot and line loading | Foundry | Foundry | TOMPW | You |
| Package build, tooling and substrate supply | OSAT | TOMPW | You | Test house |
| CP / FT programme and test hardware | TOMPW | TOMPW | Test house | You |
| Qualification evidence and reliability report | Lab / OSAT | TOMPW | You | End customer |
| Volume forecast, purchase orders and payment | You | You | TOMPW | OSAT |
| Change control, PCN / EOL notification | TOMPW | You | Foundry / OSAT | End customer |
COMMERCIAL OWNERSHIP
Who signs, and who carries the risk
Turnkey removes handoff gaps, not commercial reality. Masks, tooling, inventory and volume commitments still belong to someone, and saying who before the first order prevents most disputes.
Who places the order
YouPurchase orders for masks, wafers, package tooling and test hardware are placed by you with the supplying party. TOMPW prepares the specification and the quote basis; it does not take title of the goods.
Who carries NRE
YouMask, tooling, probe card, load board and qualification costs sit with you. They are quoted and staged before commitment so the cash profile is visible, but they are not absorbed into a unit price.
Who carries inventory risk
YouWafer, die and finished-unit inventory sits with you once built. Volume commitments made to hold a capacity slot are your commitment; TOMPW flags the exposure before you sign it.
Engineering to volume switch
JointThe switch from engineering lots to a production release is a defined gate: yield and DPPM against target, package and test hardware proven, and a signed-off qualification package. Nothing ramps before that gate.
Batch traceability
TOMPWLot, wafer and date-code traceability is maintained across foundry, assembly and test so a field issue can be traced back to a specific build. How far traceability extends depends on what each party records, and that is confirmed per programme.
PCN / EOL handling
TOMPW monitors, You decideTOMPW tracks process change notices and end-of-life notices from foundry, OSAT and material suppliers and routes them to you. Whether to accept, re-qualify or last-time-buy is your decision.
Abnormal lots and logistics
TOMPW coordinates, supplier owns the claimOut-of-spec lots, yield excursions and shipping damage are handled through the responsible party's claim process. TOMPW manages the interface and the evidence pack; the supplying party owns the commercial remedy.
Execution Notes
Commercially important details buyers usually ask later
- This service is strongest when paired with verification and backend planning early.
- IP availability and licensing path should be checked before integration commitments.
- Manufacturing fit matters during design planning, not only after RTL freeze.
Next Move
Share node, schedule and downstream requirements together
The right recommendation depends on more than one keyword. For example, package, CP, FT and sample goals often change whether MPW, NTO or a broader turnkey path makes the most sense.
Email project contextFAQ
Questions buyers ask around ASIC / SoC Design
TOMPW supports design as well as manufacturing. The practical value is continuity from specification through RTL to manufacturing execution, instead of a fragmented handoff between separate vendors. Design and tape-out planning stay under one coordinated path.
Yes, but narrow the node strategy and likely IP ecosystem early so implementation does not drift from the production target. Architecture and RTL can progress while the final foundry is confirmed, with manufacturability checked throughout.
Related Services
Adjacent steps in the same silicon program
FIRST-SILICON CONFIDENCE
Design Verification
Strengthen first-silicon confidence with structured verification, validation planning and downstream debug preparation.
BACKEND TO SIGN-OFF
Physical Design & Layout
Bridge netlist to manufacturable layout with backend planning that stays aligned with foundry rules and sign-off needs.
IP FIT BEFORE INTEGRATION PAIN
IP Cores & Licensing
Third-party semiconductor IP sales and sourcing, with process-fit review, licensing coordination and clearly scoped integration support.
ONE PARTNER · FULL DELIVERY PATH
Turnkey ASIC Solutions
Unify design support, tape-out, packaging, test, board work and delivery under one execution-facing partner.
FOUNDRY COVERAGE
Foundry profiles to compare for this path
Compare public technology profiles for ASIC / SoC Design, from advanced logic to mature analog, compound and specialty processes. PDK access, contracting route and current availability are confirmed for each project.
PLANNING TOOLS
Handoff checks and planning tools
Review declared handoff inputs with local-only checks, and keep cost and die-count estimates separate from engineering approval.
Tape-out Budget Estimator
Full program model: DPW, yield, packaging, HBM, test, NRE and volume → unit cost, price and gross margin.
Open tool →Wafer & Unit Cost Calculator
Turn a wafer run into a per-chip cost: dies per wafer, yield, packaging and test, plus a target margin.
Open tool →Third-Party IP Delivery Checker
Check third-party IP delivery views and responsibilities. Optionally match local files against a trusted manifest using SHA256, size and relative path.
Open tool →