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ASSEMBLY PATH TO SHIPPABLE PRODUCT

Packaging Support That Starts Before Wafers Arrive

TOMPW coordinates semiconductor packaging with external assembly and test providers, including Huatian and JCET. We align your die, package and test requirements with the selected provider; the factory site and process capability are confirmed for each project.

Teams moving from bare wafer to evaluated productProducts where package form factor affects electrical or thermal behaviorCustomers that need one coordinator across assembly and test suppliers
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Packaged semiconductor devices used to illustrate packaging services

QUICK ANSWER

What package families can TOMPW coordinate for a chip program?

TOMPW helps match packaging routes through external assembly providers: QFN/DFN, SOP/SSOP/SOT, QFP, BGA/LGA, ceramic or cavity packages, WLCSP, flip-chip, multi-die SiP and COB. Options require the selected factory's process, materials and tooling review. TOMPW coordinates the requirements and suppliers; the assembly provider executes manufacturing.

Can packaging be arranged for MPW wafers?

Yes, subject to review of the incoming wafer or MPW block, die layout and selected assembly route. Plan singulation, die picking, die attach, interconnect, protection and test handoff before wafers arrive.

Open Package Selection Advisor→Compare package types side by side

PACKAGE FAMILIES

Common forms TOMPW helps plan and coordinate

Package choice shapes electrical, thermal and board behavior. The ranges below are typical industry planning ranges, not TOMPW specifications.

FamilyFull nameTypical IOTypical pitchSubstrateTypical use
QFN / DFNQuad / Dual Flat No-lead6 – 1000.4 – 0.65 mmCopper leadframe with die-pad paddleLeadless with exposed-pad thermal path; common for analog, RF, mixed-signal and power devices.
SOP / SSOP / SOTSmall-outline leaded3 – 280.635 – 1.27 mmPre-plated copper leadframeLeaded, easy board assembly; sensors, low/mid-IO logic, LDO and PMIC devices.
QFPQuad Flat Packageproject-specifictooling-dependentLeadframeLeaded perimeter connections for engineering samples and board-level evaluation; body size and lead geometry require tooling review.
BGA / LGABall / Land Grid Arrayup to several hundred0.4 – 1.0 mmBT laminate or built-up substrate with solder balls / landsArea-array for higher IO density and better electrical/thermal behavior; ASIC, SoC, FPGA.
WLCSPWafer-Level Chip Scalevaries by die0.35 – 0.5 mmRedistribution layer (RDL) on the wafer itselfDie-size package with the shortest interconnect; space/power-constrained mobile and RF devices.
Flip-ChipFlip-Chip bumphighsub-150 µm bumpsBT / built-up laminate with under-bump metallizationFace-down interconnects on a package substrate or board; electrical and thermal performance must be evaluated for the actual construction.
SiP / HeterogeneousSystem-in-Packagemodule-dependent—Ceramic or laminate with multiple dice and passivesMultiple dice and passives in one module; RF front-ends, sensor hubs, power modules.
Ceramic / CavityCLCC / CQFN, CDIP, CQFP, CBGA and TO-style optionsproject-specificpackage-dependentCeramic body or metal-ceramic enclosureOpen-cavity or sealed constructions for RF, sensors and special environments. Ceramic construction alone does not establish hermeticity.
COBChip-on-Boardpad-map dependentprocess-dependentCustomer board or agreed substrateBare-die attachment and interconnect on a board or substrate, with protection and test access defined for the application.
Compare package types side by sideOpen Package Selection Advisor

Included Scope

What this service is built to handle

  • Package matching across QFN/DFN, SOP/SSOP/SOT, QFP, BGA/LGA, ceramic/cavity, WLCSP, flip-chip, multi-die SiP and COB routes
  • Prototype assembly coordination: die attach, wire bond, molding or cavity/sealing review for engineering lots
  • Wafer or MPW-block preparation, dicing, die selection and backside metallization enquiries, subject to material and process review
  • Inspection and failure analysis: 2D/3D X-ray, C-SAM/SAT, decap, cross-section and layer removal
  • Reliability and qualification path: HTOL/HAST/burn-in, ESD (HBM/CDM/Latch-up) and AEC-Q100/Q101-style automotive prep
  • Coordination with CP, FT, SLT and downstream board-level evaluation

Best Fit

Common situations where this path makes sense

  • Teams moving from bare wafer to evaluated product
  • Products where package form factor affects electrical or thermal behavior
  • Customers that need one coordinator across assembly and test suppliers

Deliverables

Typical outputs from TOMPW coordination

  • Package path recommendation inputs
  • Assembly coordination
  • Package and test handoff alignment
  • Sample delivery support

CAPABILITY DETAIL

Assembly routes we help you source

Bring the die requirements first. We help find a suitable provider and agree the build and test handoff. These options describe enquiry scope, not TOMPW-owned manufacturing lines or guaranteed supplier availability.

ASSEMBLY ROUTE01

Leadframe + wire bond

Check pad access, wire loops, die attach and mold clearance.

ASSEMBLY ROUTE02

Ceramic cavity + multi-die

Check die placement, cavity height, lid and seal requirements.

ASSEMBLY ROUTE03

Flip-chip + substrate

Check bump map, substrate routing, underfill and test access.

Original planning illustrations, not factory photographs or package drawings. Not to scale; process availability requires supplier review.

Package family selection & planning

Match leadframe, laminate and ceramic routes to the die pad layout, board footprint, thermal budget and test plan. TOMPW gathers requirements and helps identify a suitable assembly provider.

Confirm before quote

Die size, pad map, package drawing, substrate or leadframe availability, tooling and minimum lot.

Wafer preparation, dicing & die selection

Coordinate backgrind, full-wafer or MPW-block singulation, inspection and die picking. Silicon and other incoming materials need separate handling review; wafer-map selection and tape, tray or carrier delivery can be included in the agreed scope.

Confirm before quote

Incoming material and size, target thickness, street width, edge exclusions, wafer-map format and carrier.

Backside metallization

Help source wafer- or die-backside metallization when the attachment, electrical contact or heat path calls for it. The executing site reviews the material stack and its compatibility with thinning, dicing and downstream assembly.

Confirm before quote

Backside condition, required metal stack, adhesion and thickness criteria, thermal budget and attachment process.

Die attach process matching

Review conductive or insulating adhesive, die-attach film, eutectic and other attachment routes with the supplier. Selection depends on backside finish, cavity or leadframe construction, thermal needs and the device's process limits.

Confirm before quote

Die and substrate materials, attach-layer requirement, cure or reflow limits, void criteria and electrical isolation.

Wire bond & prototype assembly

Coordinate engineering-lot assembly for leadless and leaded forms. Ball or wedge bonding, wire material, molding and sample carriers are selected against the die pads and the chosen site's supported process, not from the package name alone.

Confirm before quote

Pad metallurgy and pitch, bond diagram, wire material, loop clearance, mold or cavity dimensions and sample quantity.

Ceramic, cavity & sealing routes

Help match CLCC/CQFN, CDIP, CQFP, ceramic grid-array and TO-style package options. Seam welding, alloy or glass sealing and adhesive closure need different feasibility checks; adhesive closure is not automatically a hermetic seal.

Confirm before quote

Package drawing, cavity height, seal method, leak-test limit, atmosphere, lid material and end-market acceptance criteria.

Multi-die SiP assembly

Review modules combining multiple dice, wire-bond or flip-chip interconnects and passive components on ceramic or laminate substrates. Define placement, component sourcing, protection or lid construction and module-level test access before selecting the build route.

Confirm before quote

Known-good-die evidence, die revisions, bill of materials, placement drawing, interconnect rules and module test plan.

RDL, bumping & flip-chip coordination

Route redistribution, pad remapping, copper-pillar or solder-bump and flip-chip enquiries to an appropriate provider. WLCSP and underfill choices depend on incoming wafer compatibility and the executing site's current design rules.

Confirm before quote

Current approved design-rule version, pad and bump maps, wafer condition, UBM stack, underfill and assembly qualification scope.

COB & authorized engineering rework

Help source chip-on-board attachment and interconnect for evaluation builds. Decapsulation, rewiring or remolding may support an agreed debug investigation, but can be destructive and does not restore production qualification by itself.

Confirm before quote

Board drawing, protection scheme, sample ownership and written authorization for destructive work, with an agreed stop condition.

Thermal, signal & power integrity review

Coordinate package and board review around the heat path, return paths, impedance, decoupling and PDN. Thermal or SI/PI analysis must state its geometry, material data, models and operating assumptions; the package family alone does not prove performance.

Confirm before quote

Power and frequency targets, package and board models, stackup, cooling conditions, model availability and review deliverables.

Inspection, failure analysis & reliability planning

Arrange X-ray, acoustic imaging, cross-section or decapsulation around a defined question. Coordinate stress, ESD and qualification preparation with the executing lab. A planned test flow or available equipment is not evidence that a device has passed qualification.

Confirm before quote

Sample plan, applicable test conditions, read-points, destructive-analysis consent, acceptance criteria and the issuing lab's report scope.

Test coordination

Wafer sort (CP), final test (FT) and system-level test (SLT) planning, load-board and handler alignment, and ATE platform coordination so packaged silicon is measurable and debuggable before customer evaluation.

Confirm before quote

Test specification, fixtures and program ownership, package handling, data format, limits and engineering-to-production handoff.

PROJECT SCOPES

Define the build and its handoff

A useful packaging enquiry starts with the incoming material and the evidence needed from the samples. The project quotation defines which deliverables the selected provider will supply.

MPW wafers to packaged, testable samples

Plan the handoff from an incoming wafer, MPW block or diced die to an agreed package and sample test. The assembly provider executes the build; TOMPW coordinates the material, drawing and test interfaces.

Customer inputs
  • Wafer or die material, dimensions, thickness, quantity and incoming form.
  • Die layout and street plan, pad metallurgy, bond map, pin-1 orientation and available wafer map.
  • Package outline, board or socket interface, electrical checks and required sample date.
Agreed deliverables
  • Reviewed singulation, die-pick, assembly and test handoff plan.
  • Agreed package and bond drawing revisions, material scope and sample identification.
  • Packaged samples with the inspection and electrical results specified in the order.
Confirm before release
  • Acceptance of customer-supplied material or MPW blocks, die-loss handling and minimum engineering lot.
  • Executing site, tooling and NRE, current schedule, test coverage and sample release criteria.

Packaging second-source review

Assess an alternative assembly route against the existing package, materials and acceptance plan. Matching the package family starts the review; it does not establish interchangeability.

Customer inputs
  • Current package and bond drawings, die revision, material list and available assembly records.
  • Target quantity, forecast, change restrictions and the reason for the transfer.
  • Required electrical, mechanical, thermal and reliability acceptance evidence.
Agreed deliverables
  • A comparison of process, material, drawing and test differences.
  • Supplier-reviewed tooling and pilot-build scope, with commercial terms confirmed before release.
  • A sample comparison and qualification plan for customer approval.
Confirm before release
  • Customer authority to share drawings and transfer the design, and ownership of tools and revisions.
  • Customer-supplied die, prototype and overseas-customer acceptance, minimum charges and required requalification.

Official capability references

These public capabilities support a project-specific sourcing review. A listing does not establish a TOMPW supplier relationship, project acceptance or available capacity. Official pages reviewed 29 October 2026.

Forehope Electronics

Its official product center lists QFN/QFP, BGA, flip-chip, SiP and bumping/WLP routes.

A potential second-source route for project review. Confirm the executing site, die and material compatibility, tooling, pilot quantity and acceptance plan before requesting a build.

Official capability reference (external) ↗

WHO DOES WHAT

TOMPW, the assembly house and you

TOMPW coordinates requirements, supplier selection and handoffs. Manufacturing is executed by the selected external assembly provider. Huatian and JCET are examples of providers used for this work; a group name alone does not confirm a particular site, package or process. The quotation and project scope identify the executing site and agreed deliverables. Specialist reviews below are included only when scoped.

ActivityTOMPWAssembly house / labYou
Package family selectionLeads — narrows options against die, thermal, board and test constraintsConfirms which forms it can tool and runApproves the choice against board footprint and end-market spec
Die pad / bump map reviewLeads — checks pad access, street width and bond feasibilityReturns assembly design-rule feedbackSupplies the pad or bump map and the I/O requirement
Substrate and leadframe designCoordinates — scope, vendor options and cost tradeLeads the design and owns supplyApproves stackup, material and unit cost
Wafer backgrind and dicingCoordinates — sequence, thickness and handling riskExecutesDefines target die thickness and street requirements
Die attach, wire bond and moldingCoordinates — wire type, mold compound and line loadingExecutes and owns process yieldReceives built parts and build record
Bumping, RDL and WLCSP processesCoordinates — project-scoped, confirmed before commitmentExecutes and owns wafer-level process capabilityApproves the wafer-level process and its cost impact
Thermal path planningLeads — exposed pad, spreader, via and TIM selectionProvides package-level thermal dataOwns board-side copper area and system airflow
Signal and power integrity reviewLeads the review against package breakout densityProvides package parasitics and S-parameters where availableOwns board stackup, layout and the final design decision
Inspection and failure analysisCoordinates — method choice and sample planExecutes X-ray, C-SAM, decap and cross-sectionDefines the question and releases samples
Reliability and qualificationPlans the flow, sample allocation and read-pointsExecutes stress and measurementSets the end-market standard and accepts the report
CP / FT test coordinationLeads — test plan, hardware timing and data formatExecutes the test insertionDefines the product spec, binning and DPPM target
Volume production and supplyCoordinates — forecast handoff and change controlOwns capacity, pricing and delivery commitmentOwns the forecast, purchase order and acceptance

SCOPE LIMITS

What TOMPW does not commit to on its own

  • These are supplier-matching and coordination options, not a guarantee of availability. Each project's selected factory must confirm current feasibility, materials, capacity, lead time and acceptance criteria in writing.
  • Assembly, moulding, bumping and substrate fabrication run on an assembly line, and that line's capability sets what can be quoted for a given package.
  • Substrate, leadframe and mold compound options require supplier confirmation. The quotation identifies the agreed materials, commercial scope and change-control process.
  • Board-level thermal and SI/PI behaviour depends on the customer's own stackup and layout. TOMPW reviews the design; the customer owns the final layout decision and its result.
  • Reliability stress, read-points and failure analysis are executed by the lab or assembly house. TOMPW plans and coordinates them and does not issue the qualification certificate.
  • Volume capacity must be confirmed with the selected factory. The quotation and order define TOMPW's commercial obligations, acceptance criteria and the escalation route for manufacturing issues.

THERMAL MANAGEMENT

Heat-path planning across package families

Thermal behavior is part of package selection, not an afterthought. The table below maps common heat-path approaches to package type and the kind of device they typically support. The exact resistance values depend on the package, the customer's board copper layout and the airflow in the end product.

Thermal pathBest forThermal validation considerations
Exposed die-pad (QFN/DFN)Power management, RF PA, motor driver, LED driverθJA in the tens of °C/W range, depending on PCB copper area
Heat-spreader BGA / lidHigh-power ASIC/SoC, FPGA, multi-die modulesUse package-specific thermal data with the stated PCB, TIM, heatsink and airflow conditions; package family alone does not determine thermal resistance
Thermal vias under exposed padAll QFN/DFN-style leadless packages on customer PCBPerformance depends on via geometry, copper planes, solder coverage and board construction; validate the actual board rather than assume a fixed improvement
Top-side cooling / heatsink attachHigh-TDP SoC, automotive ECU, server-class siliconDriven by TIM (thermal interface material) choice and heatsink design
WLCSP backside coolingMobile PMIC, RF front-end, small die with tight thermal envelopeDriven primarily by PCB copper area and via count

SIGNAL & POWER INTEGRITY

SI / PI knobs that matter at the package boundary

For BGA, flip-chip and high-speed packages, signal and power integrity decisions at the package boundary often determine whether the design works on the customer board. The topics below are the recurring ones for package-level SI/PI review.

Return-path discipline in BGA fanout

For BGA and flip-chip packages, ground/power return paths under the die need continuous reference planes. Breaks in the return path cause resonant impedance spikes that show up as SI/PI issues at high speed.

Power-delivery network (PDN) decoupling

Bulk, mid-frequency and high-frequency decoupling are placed as close to the die pads as possible, with package-level and on-die capacitance layered. For high-current transients, VRM loop bandwidth and bulk capacitor ESR matter as much as the on-board layout.

Impedance-controlled routing

DDR, PCIe, USB, MIPI, Ethernet and SerDes all require controlled single-ended or differential impedance. Stackup choice (core/prepreg thickness, copper weight) sets the achievable impedance; the layout follows the stackup target with verified tolerance.

Crosstalk mitigation

Aggressor/victim spacing, return paths and differential pair symmetry affect crosstalk. For dense BGA breakouts, compare dog-bone fanout and via-in-pad against ball pitch, fabricator design rules and available routing layers rather than assume a fixed density gain.

High-current / low-impedance power planes

Power-hungry SoCs need wide copper pours or multiple planes stitched with sufficient vias. For packages with exposed-pad current paths, via placement under the pad needs to balance current-carrying capacity vs thermal relief for solder joint reliability.

ENGAGEMENT PATTERNS

Typical shapes of packaging work

The examples below describe representative forms of engagement. They are illustrative of the type of work and are not specific client records, names, volumes or results.

RF / mixed-signal QFN prototype

For an RF prototype in QFN, review pad access, wire material, grounding and package parasitics with the assembly provider. Define the singulation, molding and final-test handoff before releasing the build.

BGA field-return failure analysis

For an intermittent field return, agree the failure hypothesis and sample plan first. Non-destructive X-ray or C-SAM may guide a subsequent destructive analysis; a suspected anomaly is not a confirmed root cause without supporting evidence.

Power IC DFN wire-bond prototype

For a power-management device in DFN, check wafer thickness, die handling, bond material and the exposed-pad path with the OSAT. Define which thermal and electrical measurements the customer needs from assembled samples.

Automotive-sensor reliability prep

For an automotive sensor, identify the applicable qualification requirements, package construction and test samples with the customer and executing lab. Planning a test flow is not evidence that a device has completed qualification.

BGA fanout SI/PI review before customer release

Before a BGA board release, review the breakout, reference planes and PDN against package models and board assumptions. Agree the review scope, model availability and acceptance criteria rather than infer performance from the package name.

Package change during MPW-to-mask transition

If a program considers moving from QFN to WLCSP, assess pad layout, redistribution, board assembly and qualification impacts before committing. A package change may require design changes; it is not a drop-in manufacturing substitution.

SiP module for a sensor hub

For a module combining an ASIC, an MCU and passives, establish die compatibility, known-good-die evidence, substrate requirements and test access. Confirm the assembly site's process and module-level acceptance plan before selecting a SiP route.

RELATED GUIDES

Go deeper on each packaging decision

Each guide below covers one decision in the assembly plan, with the cost, reliability and lead-time trade-offs that go with it. Browse the full packaging topic →

Execution Notes

Commercially important details buyers usually ask later

  • Package choice should be aligned with test, board and end-market qualification needs from the start.
  • The selected assembly site confirms feasibility against wire type, mold compound, tooling and the agreed project requirements.
  • Inspection and failure analysis can be arranged as standalone work or as part of a broader debug engagement.
  • Package choice is often driven by board, thermal and qualification constraints rather than by the foundry alone, so it should be settled alongside node selection.

Next Move

Send the inputs that determine feasibility

A package name alone is not enough for a supplier to confirm a build. For an initial review, describe the following without sending confidential design files until the sharing route is agreed.

  • Incoming die: material, length, width, thickness, wafer or diced form and quantity.
  • Interconnect: pad/pin map, units, pad metallurgy, pitch, orientation and pin-1 reference.
  • Package constraints: footprint, thermal or RF targets, cavity/lid needs and seal/leak criteria if applicable.
  • Acceptance: test plan, reliability requirements, sample and volume targets, and required delivery window.
Check pad/pin inputs before enquiryEmail project context

FAQ

Questions buyers ask around packaging

Yes. Packaging is often the next decision after first silicon, and planning it before wafers are delivered avoids idle time and rework once samples are in hand.

TOMPW helps match QFN/DFN, SOP/SSOP/SOT, QFP, BGA/LGA, ceramic or cavity packages, WLCSP, flip-chip, multi-die SiP and COB routes through external providers. Every route requires project-specific tooling, material and process confirmation. A ceramic body or adhesive lid does not by itself establish hermeticity; sealed-package enquiries need agreed seal and leak-test criteria.

Yes. TOMPW coordinates requirements and assembly sourcing with external providers, including Huatian and JCET. The selected factory site confirms package compatibility, tooling and material availability for the specific project; the quotation defines the deliverables and responsibilities.

Yes. Start with the current package and bond drawings, material list, die revision, sample quantity and acceptance requirements. TOMPW can coordinate a supplier comparison and pilot-build scope. The customer and executing provider must approve any material, process or drawing changes and the evidence needed before production release.

Yes. 2D/3D X-ray, C-SAM/SAT, decapsulation, cross-section and layer removal can be arranged on their own or as part of a broader debug engagement.

TOMPW can help structure reliability stress, burn-in, ESD and automotive qualification preparation with a defined sample and test plan. The executing lab confirms applicable conditions and issues the report; coordination is not a claim that the device is already qualified.

Package choice, sample readiness and qualification flow are downstream decisions that shape cost and schedule. Planning them early avoids idle time after wafers return and prevents rework once the first samples are already in hand.

Common paths include exposed die-pad with thermal vias, heat-spreader BGA with lid attach, top-side heatsink with TIM, and WLCSP backside cooling. The right path depends on package type, TDP envelope and customer-board copper area.

Review the signal return paths, controlled-impedance routing and PDN against package and board models. The choice between via-in-pad and dog-bone fanout depends on ball pitch, routing layers and fabricator rules, so it should be evaluated for the actual design.

Standard BT laminate is sufficient for most BGA up to mid-density. Built-up (ABF/Ajinomoto build-up film) substrates are needed for fine-pitch flip-chip and high-I/O ASIC/SoC packages, and for high-speed signal routing. Substrate vendor selection is part of the package sourcing conversation.

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Test & Product Engineering visual

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Connect CP, FT and reliability planning so packaged silicon is measurable, debuggable and ready for customer evaluation.

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BOARD-LEVEL PRODUCTIZATION

PCB Design & Manufacturing

Support evaluation boards, demo boards and production-minded PCB work that connects packaged silicon to a usable system.

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ONE PARTNER · FULL DELIVERY PATH

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Unify design support, tape-out, packaging, test, board work and delivery under one execution-facing partner.

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Upstream

IP sourcing & licensing →

Downstream

Test & product engineering →

Pairs with

Chip evaluation, demo & test boards (HDI ATE load boards) →

FOUNDRY COVERAGE

Foundries TOMPW coordinates for this path

Packaging engagements are planned across TOMPW's foundry network, from advanced logic to mature analog, compound and specialty processes.

TSMCUMCGlobalFoundriesSMICTowerHHGraceams OSRAMX-FAB
View all foundry profiles →

PLANNING TOOLS

Handoff checks and packaging planning tools

Review pad-to-pin inputs and a schematic bond map, inspect RF files, or compare package and unit-cost assumptions before supplier review.

Package Selection Advisor

Match QFN, BGA, WLCSP, Flip-Chip, SiP or legacy leaded packages to your IO, power, RF, cost and form-factor constraints.

Open tool →

Wafer & Unit Cost Calculator

Turn a wafer run into a per-chip cost: dies per wafer, yield, packaging and test, plus a target margin.

Open tool →

Packaging Input Checker & Bond Sketch

Check pad-to-pin mapping and orientation, compare packaging revisions and overlay 2D bond sketches before an OSAT handoff.

Open tool →

Touchstone S-Parameter Viewer

View one- and two-port S-parameter magnitude and phase. Compare files only with matching frequency grids, reference resistance and declared conditions.

Open tool →
Plan an MPW run across our foundry network →