CP · FT · RELIABILITY

Test Planning That Protects the Value of Each Tape-Out

Good silicon still needs a workable test path. TOMPW helps customers think through wafer sort, final test, load board needs and reliability preparation as part of the total delivery chain.

Programs preparing engineering samples for end-customer reviewProducts needing CP/FT planning before assembly startsTeams that do not want test to become a last-minute bottleneck

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Packaged chip image used for product engineering and test service

QUICK ANSWER

Does TOMPW coordinate wafer sort (CP), final test (FT) and reliability prep?

Yes. Test planning is part of the delivery chain, not a late-stage separate task. We coordinate CP, FT, system-level test, reliability prep (HTOL / HAST / ESD), yield analysis and failure-analysis handoff so packaged silicon is measurable and debuggable before customer evaluation.

Which test platforms can TOMPW work with?

TOMPW is not an ATE vendor. We coordinate with V93000-class, Teradyne, Chroma and similar mixed-signal / RF platforms, plus bench setups for RF and high-speed validation. The right platform is selected per project, not from a fixed list.

Discuss test planning→Open Test Cost & Yield tool

TEST FLOW

Wafer sort to customer samples, all coordinated

A coherent test path runs from wafer probe through reliability prep. The list below is the typical sequence; each step can be scoped as standalone work or as part of a broader delivery plan.

STEP 01
Test strategy & program planning
CP/FT split, binning, DPPM target
STEP 02
CP — wafer sort
Probe card, prober interface, alignment
STEP 03
FT — final test
Load board, ATE platform, test time
STEP 04
Test program bring-up
Pattern translation, shmoo, characterization
STEP 05
Reliability prep
HTOL, HAST, ESD, burn-in planning
STEP 06
Yield analysis & DPPM tracking
Per-lot trends, outlier lot review
STEP 07
System-level & board-level test
SLT, bench validation
STEP 08
Failure analysis handoff
X-ray, C-SAM, decap, cross-section, FA

CP VS FT

Two different test stages, two different problems

Wafer sort and final test use different hardware, carry different lead times and close on different gates. Treating them as one line item is the most common reason a test plan cannot be quoted or meets its date.

CP — Wafer sort / circuit probe

Which die are worth spending package money on?

Test hardware required

Probe card designed from the die pad layout and street plan
Prober interface and touchdown / alignment recipe
Wafer-level temperature option if the screen needs hot or cold corners

What we need from you

Pad or bump map, die size and street width
The list of parameters that must be screened at wafer level
DFT mode list and pattern set, if scan or BIST is available
Expected yield range and the CP-to-FT yield-correlation assumption

What you get back

Wafer map with per-die pass/fail and bin assignment
Parametric datalog for every touched die
Inkless mapping file handed to assembly so only good die are packaged

Exit gate: CP yield against target and coverage sign-off, before wafers release to backgrind and assembly.

FT — Final test on packaged parts

Does the finished part meet the product spec it ships against?

Test hardware required

Load board matched to the package pin-out
Socket or contactor, and handler or pick-and-place interface
ATE platform with the right mixed-signal, RF or digital capability

What we need from you

Package pin-out and the product specification
Binning definition — what gets shipped as what
Voltage and temperature corners the part must be tested across
Test-time budget per unit, which drives cost at volume

What you get back

Unit-level pass/fail result with bin assignment
STDF-format datalog for every tested unit
Lot yield summary and DPPM trend against the agreed target

Exit gate: FT yield and DPPM against target, and sample release approved, before parts ship for customer evaluation.

ACROSS BOTH STAGES

The engineering work buyers most often assume is included

Test program development

Pattern translation from simulation vectors, shmoo and characterization runs, and datalog-driven debug. Bring-up goes fastest when the package, pin map and platform are already locked rather than still moving.

DFT inputs

Scan chains, BIST and boundary scan decide how much of the device a test program can actually reach. TOMPW needs the DFT mode list and pattern set to scope coverage; where DFT is thin, achievable coverage is lower and that limit is stated up front rather than discovered at bring-up.

Probe card and load board

These are the two long-lead items in any test plan, and both are frequently longer than the wafer fab cycle. They are scoped from the pad map and package pin-out, and their lead time is why test planning belongs in the first commercial conversation.

Volume test and multi-site

At volume, ATE seconds per unit dominate unit cost. Multi-site parallelism and test-list trimming are the two levers that matter, and both are planned against the test-time budget rather than added after the program is frozen.

Data formats

Two files carry everything downstream: the wafer map from CP and the STDF datalog from each test insertion. Agreeing on format, naming and delivery cadence before first silicon is what keeps yield analysis from stalling on file wrangling.

Yield and DPPM analysis

Per-lot yield review, parametric trending and outlier-lot analysis, feeding back into test program tuning and into upstream process conversations. DPPM targets are set against the end-product spec, not against a generic benchmark.

Included Scope

What this service is built to handle

Coordination for wafer sort and final test planning
Load board and demo-board related preparation inputs
Reliability and environmental test support path
Alignment with package, board and customer-evaluation milestones

Best Fit

Common situations where this path makes sense

Programs preparing engineering samples for end-customer review
Products needing CP/FT planning before assembly starts
Teams that do not want test to become a last-minute bottleneck

Deliverables

Typical outputs from TOMPW coordination

Test path review
CP and FT coordination inputs
Reliability planning support
Board-level evaluation alignment

CAPABILITY DETAIL

From test planning to samples and qualification evidence

Test strategy & program planning

Early definition of the test path: which device parameters must be screened at CP vs FT, how production-level binning affects probe time and yield, and what failure-mode coverage the test program needs to deliver before customer samples ship.

Wafer sort (CP) coordination

Probe card design inputs, prober/handler interface, alignment to die-level pad layout and street plan. Coordinates with wafer backgrind/dicing and probe-card supply timing so CP doesn't sit idle waiting on hardware.

Final test (FT) & ATE coordination

Load board and socket planning, ATE platform selection (V93000, Teradyne, STS, etc. — chosen per project), test-time budget, and binning definition aligned with the product spec. Coordinated with package-level test access.

Test program development & bring-up

Pattern translation from simulation vectors, shmoo and characterization support, datalog-driven debug and DPPM target setting. Bring-up is most efficient when the package, pin map and ATE platform are already locked.

Reliability & qualification prep

HTOL, HAST, temperature cycling, ESD (HBM/CDM/Latch-up) and burn-in planning, sample allocation and read-point scheduling. Aligned with end-market requirements (consumer, industrial, automotive per AEC-Q100/Q101-style flows).

System-level & board-level test alignment

For products that ship as a module or board, plan SLT and bench-level validation alongside the FT program so coverage extends beyond the silicon die. Useful for RF and mixed-signal devices where final behavior emerges at the board level.

Yield analysis & DPPM tracking

Per-lot yield review, parametric tracking, outlier lot analysis and continuous DPPM trending. Feedback loop into test program tuning and into upstream wafer-process improvement conversations with the foundry.

Failure analysis handoff

When a part fails CP/FT or returns from the field, hand off cleanly to FA: 2D/3D X-ray, C-SAM, decap, cross-section, nanoprobing, FIB or TEM as needed. Coordinated with the packaging FA path so the same package isn't analyzed twice.

PROJECT SCOPES

Agree the inputs, evidence and release criteria

Define the test or laboratory question before samples move. TOMPW coordinates the review and handoffs; the selected provider confirms the methods, execution site and quoted deliverables.

CP / FT development & production transfer

Scope a new test insertion or transfer an existing program to a selected test provider. Agree the platform, hardware, coverage, pilot-lot correlation and release criteria before transferring the program into production.

Customer inputs: Device specification, pad and pin maps, DFT modes, vectors and test limits.
Existing program and datalogs, known-good and failing samples, and temperature corners where available.
Package or wafer format, sample and production quantities, test-time target and release date.
Agreed deliverables: An agreed CP/FT test list, coverage limits, binning and hardware plan.
Program bring-up and pilot-lot correlation results, with program and hardware ownership defined in the scope.
Wafer maps, per-unit results, STDF or another agreed data format, and lot summaries for the quoted insertions.
An agreed production handoff record covering program revision, hardware setup, release criteria and ongoing yield/data review.
Confirm before release: Executing site and tester, probe card or load board/socket availability, engineering-lot acceptance and development charges.
Access to source programs, licenses and vectors; data rights, transfer support, test time and sample release criteria.

Failure analysis & reliability verification

Start with a failure question or an application-specific reliability requirement. Coordinate the laboratory plan, sample allocation and read-point tests, then review the evidence and any follow-up verification with the customer.

Customer inputs: Failure symptoms and history, affected lot and package/board revisions, failing samples and good controls.
Operating and stress conditions, applicable standard and revision, test limits and required report language.
Design-sharing permission, sample budget and explicit authorization for any destructive analysis.
Agreed deliverables: An agreed analysis or stress matrix, sample counts, read points and stage-by-stage approval plan.
Laboratory reports and agreed raw images or measurements, with sample identity and test conditions.
A distinction between observed defects, supported root-cause conclusions and open questions, plus a retest plan where needed.
Confirm before release: Executing laboratory, method and accreditation scope, customer recognition, schedule and read-point electrical testing.
Destructive-analysis limits, remaining-sample disposition, data ownership and the conditions for further work. Qualification follows the agreed evidence and customer acceptance process.

Official capability references

Use these official descriptions to assess possible test and laboratory routes. Listing a provider does not establish a TOMPW relationship, project acceptance or available capacity. Official pages reviewed 29 October 2026.

KYEC

Its official service page lists wafer probing, final test, burn-in and system-level testing.

For a CP/FT route review, confirm the actual tester and site, device interface, development scope, lot size and data deliverables.

Official capability reference (external) ↗

iST — Integrated Service Technology

Its official board-level reliability and FA page describes X-ray, SAT, thermal EMMI and follow-up physical analysis.

For a reliability-failure investigation, define the board and package history, analysis stages, executing lab and any repeat verification.

Official capability reference (external) ↗

MA-tek

Its official service directory covers reliability, non-destructive inspection, electrical failure analysis and material analysis.

For a failed-sample investigation, agree the method, evidence required, sample handling and authorization before destructive work.

Official capability reference (external) ↗

ENGAGEMENT PATTERNS

Typical shapes of test and product engineering work

The examples below describe representative forms of engagement. They are illustrative of the type of work and are not specific client records, names, volumes or results.

MPW-to-NTO test program port

If a design validated on MPW needs a production test path before NTO, scope pattern translation, characterization shmoos and probe-card revisions with the test provider. Agree coverage and correlation gates before releasing the program.

Multi-site test time reduction

If single-site FT costs exceed the target, evaluate multi-site parallelism, test coverage and load-board changes with the provider. Measure the correlation, test-time and yield effects on a pilot lot before deciding on a production change.

Automotive-grade reliability alignment

For a sensor targeting a vehicle application, identify the applicable AEC-Q100 or AEC-Q101 requirements with the customer and lab. Define stress conditions, sample counts, read-point tests and acceptance criteria before work starts; planning alone does not establish qualification.

RF bench validation alongside FT

If an RF device needs bench validation alongside FT, define the instruments, fixtures, calibration and automation for the required measurements. Agree sample identity and correlation criteria so bench and FT results can be compared.

RELATED GUIDES

Go deeper on each test decision

Each guide below covers one decision in the test plan, with the cost and schedule trade-offs that go with it. Browse the full test & DFT topic →

Execution Notes

Commercially important details buyers usually ask later

Source material explicitly lists CP, FT, load board, demo board, reliability and environmental test support.
Test planning is most effective when defined before package lock, not after.
This site positions TOMPW as a program coordinator, not as a standalone tester brand.

Next Move

Send device, package and end-market context together

Test scope changes sharply with end market (consumer vs automotive) and with package (QFN vs BGA). Sharing that context up front keeps the test plan honest about lead time and cost.

Email test context

FAQ

Questions buyers ask around test and product engineering

Sample delivery slips, debug slows and customer evaluation is delayed. Load-board and probe-card lead times are often longer than the wafer fab cycle, so test belongs in the commercial conversation early — not hidden until after contract signing, when options are already limited.

No. The coordination can include wafer sort (CP), final test (FT), system-level test (SLT), reliability and qualification prep, yield analysis and FA handoff. TOMPW treats test as part of the delivery chain, not a separate late-stage task.

Yes. Test access, package pin-out and load-board layout all interact. Coordinating CP/FT planning with package planning avoids pad-access issues and re-spins of either the test hardware or the package.

Yes. Share the failure history or verification requirement, available samples, package or board revision and required report. TOMPW can coordinate a laboratory review and staged plan. The selected lab confirms methods, sample counts, accreditation scope and schedule; destructive work needs explicit authorization, and qualification depends on the agreed evidence and customer acceptance.

TOMPW is not an ATE vendor. Coordination commonly covers V93000-class, Teradyne, Chroma and similar mixed-signal/RF platforms, plus bench-level setups for RF and high-speed validation. The right platform is selected per project, not from a fixed list.

Yes. Consumer and industrial reliability plans use a lighter version of the same HTOL/HAST/ESD frameworks, with sample size and read-points scaled to the application. AEC-Q100/Q101-style automotive prep is added only when the device is targeting vehicle platforms.

CP exists to stop you paying to package die that were never good. Skipping it can be reasonable at very small sample counts or when the package is cheap relative to the die, but it moves all yield risk to final test, where a failing part has already absorbed package and assembly cost. The trade is worth doing arithmetically against your die cost, package cost and expected yield — not by default.

The two files that matter are the wafer map from CP, which shows which die passed and how they binned, and the STDF datalog from each test insertion, which carries the parametric result per unit. Agreeing on format, naming and delivery cadence before first silicon is what keeps yield analysis from stalling on file handling later.

Per-lot yield review with parametric tracking and outlier lot analysis, plus a continuous feedback loop into test program tuning and into upstream wafer-process conversations with the foundry. DPPM targets are set against the end-product spec, not generic benchmarks.

Related Services

Adjacent steps in the same silicon program

ASSEMBLY PATH TO SHIPPABLE PRODUCT

Semiconductor Packaging

Semiconductor packaging through external assembly and test providers, with TOMPW coordinating package selection, supplier review and assembly-to-test handoff.

Teams moving from bare wafer to evaluated productProducts where package form factor affects electrical or thermal behavior

View service

BOARD-LEVEL PRODUCTIZATION

PCB Design & Manufacturing

Support evaluation boards, demo boards and production-minded PCB work that connects packaged silicon to a usable system.

ASIC or module teams needing demo hardwarePrograms preparing customer evaluation kits

View service

ONE COORDINATED CHAIN

Supply Chain & Logistics

Simplify handoffs across fabs, packaging houses, test providers and international delivery partners.

Global customers sourcing through Asia manufacturing partnersPrograms with multiple packaging and test handoffs

View service

ONE PARTNER · FULL DELIVERY PATH

Turnkey ASIC Solutions

Unify design support, tape-out, packaging, test, board work and delivery under one execution-facing partner.

Companies building their first custom chip supply chainGlobal teams wanting a single execution partner in Asia

View service

Upstream

Semiconductor packaging →

Upstream

IP sourcing & licensing →

Pairs with

Chip evaluation, demo & test boards →

FOUNDRY COVERAGE

Foundries TOMPW coordinates for this path

Test planning is foundry-agnostic in principle but tightly tied to wafer probe and reliability infrastructure in practice. The foundries below are the ones most often involved in programs that run through TOMPW coordination.

TSMC UMC GlobalFoundries SMIC Tower HHGrace ams OSRAM X-FAB

View all foundry profiles →

PLANNING TOOLS

Test-data checks and planning tools

Inspect explicit die-status maps and matched S-parameter data, then model test cost and yield assumptions separately.

Test Planning That Protects the Value of Each Tape-Out

Does TOMPW coordinate wafer sort (CP), final test (FT) and reliability prep?

Which test platforms can TOMPW work with?