LOWER NRE · FASTER FIRST SILICON
MPW Shuttle Access for Early Silicon Programs
Use multi-project wafer runs to validate designs without committing to a dedicated mask set. TOMPW helps teams compare node fit, public shuttle timing, tape-out readiness and downstream package or test implications before locking a slot.
Included Scope
What this service is built to handle
- Shared-mask shuttle entry for prototype and low-volume programs
- Multi-foundry window visibility across TSMC, UMC, SMIC, GlobalFoundries and selected specialty platforms
- Tape-out package review, foundry communication and milestone tracking
- Commercial and operations coordination from slot selection into wafer delivery
Best Fit
Common situations where this path makes sense
- Prototype ASIC or SoC validation
- Sensor, analog and mixed-signal proof-of-concept silicon
- Teams testing market demand or customer sampling before full production commitment
Deliverables
Typical outputs from TOMPW coordination
- Shuttle window and node alignment
- Tape-out checklist review
- Foundry submission coordination
- Wafer delivery timeline and status communication
Execution Notes
Commercially important details buyers usually ask later
- Standard coverage in source material spans 12nm to 3um, with below-7nm handled case by case.
- Common platforms include CMOS, BCD, SOI and selected specialty processes.
- Public shuttle calendars usually cluster around recurring month windows rather than one-off opportunities. Typical reference months include spring and autumn slots for advanced-node MPW, plus broader January to December coverage on selected 16nm, 28nm and mature mixed-signal platforms.
- Public programs from TSMC, UMC and GlobalFoundries also show that availability differs by node, operator and submission rule. Some platforms run only twice a year, while others offer multiple windows across the year.
- Published shuttle dates are normally GDS submission deadlines rather than wafer-out dates. Registration, export-control review, PO timing and package or test scope need to be aligned earlier, so final slot confirmation should be handled by email or direct project discussion.
Next Move
Share node, schedule and downstream requirements together
The right recommendation depends on more than one keyword. For example, package, CP, FT and sample goals often change whether MPW, NTO or a broader turnkey path makes the most sense.
Email project contextHOW MPW SCHEDULING WORKS
From shared mask to a confirmed shuttle slot
A multi-project wafer run places several customer designs on one mask set, so each team pays only for its portion of the wafer. Most teams use MPW for first silicon, architecture validation, early customer sampling or low-volume research — anywhere the goal is learning rather than immediate high-volume production.
Shuttles follow a monthly or quarterly cadence that depends on foundry, node, process maturity and demand. Missing a tape-out deadline usually means waiting for the next window, so slot selection and downstream package or test planning should start early.
FAQ
Questions buyers ask around MPW / Fab Shuttle
Choose MPW when your priority is low-cost first silicon and design learning rather than volume efficiency. It is the standard entry point for prototypes, design validation and early customer sampling before committing to a dedicated full-mask production run.
No. TOMPW can also review your tape-out package, coordinate foundry communication and extend the flow into packaging, test and logistics when needed. Most customers use it as an execution partner, not only a wafer-order channel.
Related Services
Adjacent steps in the same silicon program
PRODUCTION RAMP · DEDICATED MASK SET
Full Mask / Production Foundry
Move validated designs into dedicated mask production with yield, volume and supply planning support.
ASSEMBLY PATH TO SHIPPABLE PRODUCT
Semiconductor Packaging
Plan package type, prototype assembly, inspection and qualification early so silicon delivery does not stall after wafer completion.
CP · FT · RELIABILITY
Test & Product Engineering
Connect CP, FT and reliability planning so packaged silicon is measurable, debuggable and ready for customer evaluation.
ONE PARTNER · FULL DELIVERY PATH
Turnkey ASIC Solutions
Unify design support, tape-out, packaging, test, board work and delivery under one execution-facing partner.
FOUNDRY COVERAGE
Foundries TOMPW coordinates for this path
MPW / Fab Shuttleengagements are planned across TOMPW's foundry network, from advanced logic to mature analog, compound and specialty processes.