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Global semiconductor delivery

Free planning tool

Tape-out Budget Estimator

A consolidated cost model for an ASIC program — from dies per wafer and yield through packaging, HBM, test and one-time NRE, down to unit cost, price and program gross margin. Built for early business cases and customer pitches.

Process node
Yield model

Estimated unit cost

$16.88

Price @ 45% margin: $24.48

Gross DPW

633

Net die

520

Yield

82.1%

Wafer $/die

$15.38

Pkg $/die

$1.00

HBM $/die

$0.00

Test $/die

$0.50

Unit cost

$16.88

Program economics

Program cost

$2,188,462

Revenue

$2,448,269

Gross margin

$259,808

10.6%

Illustrative only. NRE/mask, HBM and packaging costs vary widely by supplier and volume — use as a sanity check, then confirm with foundry and OSAT quotes.

Export

What feeds the model

  • Unit cost = wafer $/die (wafer cost ÷ net die) + packaging + HBM + test.
  • Program cost = NRE + volume × unit cost; revenue = volume × price.
  • Margins improve sharply once volume amortizes NRE — the classic tape-out economics story.

Need a defensible quote for a real program? Talk to our team for foundry- and OSAT-verified numbers.