COST RANGES
What a tape-out programme actually costs
Compare 6 semiconductor cost categories using industry reference ranges, cost drivers and published price sources. These ranges are for budget planning, not a quotation. A project-specific quote depends on the process node, die size, package, test scope, volume and production window.
These are industry reference ranges, not a quotation and not an offer.
- Every band on this page is deliberately wide. It is published so you can sanity-check whether a programme is realistic before you write to anyone — not so you can budget against it.
- Actual pricing moves with the season and with capacity. Foundry and OSAT utilisation changes month to month, and a window that is cheap in a soft quarter can be materially more expensive in a tight one.
- Mask, substrate, leadframe, gold, copper and tester-time costs all move independently of the node you chose.
- Currency movement matters: most foundry pricing is denominated in US dollars, so a non-USD budget carries its own variance on top of everything above.
- Minimum-participation rules apply. Several published shuttle programmes only launch once a minimum number of paid seats or a minimum total area is reached, and they reserve the right to change or drop a run.
- Export-control screening can change both the route and the cost, or in some cases make a programme not viable at all.
- Nothing here is a fixed price, a guaranteed availability, or a committed delivery date. Only a written quotation issued for your project carries any of those.
- Written quotations are normally valid for a limited period — typically around 30 days — because the underlying foundry and OSAT inputs change.
REFERENCE RANGES
Industry ranges by cost line
Read the “why the range is this wide” column before you use a number. The spread is the information — it tells you which input you need to pin down first.
MPW and prototype shuttle seats
A shuttle seat buys a fixed block of reticle area on a shared mask set. Price follows the node first, then the area you take.
| Scope | Reference range | Basis | Why the range is this wide |
|---|---|---|---|
| MPW seat — mature node (≥180nm) | US$3,000 – $30,000 | per block / seat, minimum area | Mature shuttles run often and minimum areas can be well under 1 mm² at research foundries, while a large multi-project block on a commercial 180nm BCD platform sits at the top of the band. |
| MPW seat — 130nm to 55nm | US$8,000 – $80,000 | per block / seat | Mask layer count, metal stack and optional modules (eNVM, HV, RF) move the number by an order of magnitude inside this node band alone. |
| MPW seat — 40nm to 28nm | US$25,000 – $200,000 | per block / seat | Block sizes are small at these nodes, so a 10 mm² die can require several blocks; multi-block pricing and reticle utilisation dominate. |
| MPW seat — 22nm and below (FDSOI / FinFET) | US$50,000 – $400,000 | per block / seat | Fewer windows per year, minimum participation rules, mandatory qualification and much higher mask costs all push the floor up. |
| Published per-area MPW price (research foundry price list) | €900 – €9,000 per mm² | per mm² of occupied area | A real published anchor: a European research foundry's 2026 price list runs from roughly €900/mm² for an interposer module to about €9,000/mm² for a photonic BiCMOS platform, with 130nm BiCMOS in the €6,300–€7,300/mm² range. Minimum area starts at about 0.8 mm² on selected runs. |
Mask sets and full-mask NRE
A dedicated reticle set is where prototype economics change completely. This is the number that separates MPW from full mask.
| Scope | Reference range | Basis | Why the range is this wide |
|---|---|---|---|
| Full mask set — ≥180nm | US$60,000 – $500,000 | one mask set | Layer count and wafer size drive it; a simple 180nm CMOS set and a 180nm BCD set with HV and eNVM options are not comparable. |
| Full mask set — 130nm to 55nm | US$150,000 – $800,000 | one mask set | More mask layers, tighter OPC and more expensive reticle blanks at each step down. |
| Full mask set — 40nm / 28nm | US$300,000 – $1,500,000 | one mask set | Double and triple patterning, plus more masks per layer, make this the first band where mask cost becomes a board-level decision. |
| Full mask set — 16nm and below (FinFET) | US$1,000,000 – $8,000,000 | one mask set | EUV or multi-patterning layer counts, plus mandatory design-rule and DFM closure effort before tape-out. |
| Full mask set — 3nm class | US$10,000,000 – $25,000,000 | one mask set, industry commentary | Widely quoted industry figures for leading-edge tape-outs. Only relevant for very high-volume programmes; quoted here so the step from 28nm is visible, not because it is a typical project. |
Wafer price
Wafer cost follows node, wafer size and process options. It is quoted per wafer and converted into cost-per-die by yield and die count.
| Scope | Reference range | Basis | Why the range is this wide |
|---|---|---|---|
| 200mm mature wafer (≥180nm) | US$800 – $6,000 | per wafer | Simple CMOS sits low; BCD, HV, eNVM, SOI and thick-metal options add process steps and push the price up. |
| 300mm mainstream wafer (90nm – 28nm) | US$3,000 – $12,000 | per wafer | Node, metal stack and capacity utilisation at the time of the run. |
| 300mm advanced wafer (≤16nm) | US$9,000 – $25,000+ | per wafer | Leading-edge wafer pricing is negotiated against long-term commitments, so walk-up prices sit at the top of the band. |
Packaging and test
Packaging and test split into one-off engineering (development, hardware, program) and a per-part cost that follows volume.
| Scope | Reference range | Basis | Why the range is this wide |
|---|---|---|---|
| Package development NRE | US$5,000 – $150,000 | one-off per package | A standard QFN in an existing outline is cheap; a new cavity, lid, substrate design or qualified automotive flow is not. |
| Assembly — conventional package | US$0.05 – $3.00 | per part | Leadframe parts at volume sit at the bottom; low-volume, gold-wire, thick-wire or hermetic variants sit at the top. |
| Assembly — advanced package (FC-BGA, fan-out, 2.5D) | US$1.00 – $60.00 | per part | Substrate size, layer count, bump pitch, thermal solution and known-good-die yield move this by more than 10×. |
| Test program development | US$10,000 – $250,000 | one-off per product | A scan-only digital program is cheap; mixed-signal, RF or multi-site programs with load-board and probe-card hardware are not. |
| Test — per part | US$0.02 – $5.00 | per part | Test time is the driver: seconds on a mature digital tester versus minutes of mixed-signal trimming on an expensive platform. |
| ATE platform rate | US$200 – $3,000 per hour | per tester hour | Older mainstream testers sit near the bottom; high-pin-count advanced SoC testers sit at the top. |
IP licensing
IP is usually licence fee plus royalty, and the two are negotiated together. The spread across IP categories is wider than any other line item here.
| Scope | Reference range | Basis | Why the range is this wide |
|---|---|---|---|
| IP licence fee | US$10,000 – $2,000,000 | per block, per project or per licence term | A small analog or interface block and a high-speed SerDes or processor core differ by two orders of magnitude. |
| IP royalty | 0.25% – 5% of ASP, or US$0.01 – $5.00 per unit | per shipped unit | Commodity IP is licensed at fractions of a cent; differentiated high-speed or processor IP is licensed as a percentage of chip price. |
| Annual support and maintenance | 15% – 25% of licence fee | per year | Standard practice across the IP industry; sometimes bundled into a multi-year licence instead of billed separately. |
Engineering and coordination
Design, physical implementation and programme coordination are quoted as NRE against a defined scope, or as a share of the underlying foundry spend.
| Scope | Reference range | Basis | Why the range is this wide |
|---|---|---|---|
| Design / implementation / turnkey NRE | US$30,000 – $2,000,000+ | per programme | A RTL handoff with verification support and a full concept-to-silicon turnkey programme are different scopes entirely. |
| Programme coordination and access service | 5% – 25% of underlying foundry spend | per programme | Depends on how much is handled: seat reservation and logistics only, versus full tape-out management, packaging, test and delivery. |
WHAT MOVES THE NUMBER
Ten inputs that decide where you land in the range
Two projects on the same node can sit at opposite ends of the same band. These are the inputs that do it — and the ones worth answering before asking anyone for a price.
- 01Process node and wafer size
- 02Die size, and how many shuttle blocks it needs
- 03Metal layer count and optional process modules (HV, RF, eNVM, SOI, MEMS)
- 04Yield assumptions and how much reticle area is actually usable
- 05Seasonality and foundry capacity utilisation at the time of the run
- 06How full the shuttle is — several published programmes only launch once a minimum number of seats or a minimum area is filled
- 07Volume commitments and whether the price is a walk-up spot price or part of a longer agreement
- 08Currency movement, and the price of mask blanks, substrates, leadframes and gold or copper
- 09Packaging and test house choice, and the qualification grade required (consumer, industrial, automotive)
- 10Export-control screening outcome, which can change both the route and the cost
CHECK IT YOURSELF
Published sources behind these ranges
Where a foundry publishes its own numbers or its own conditions, we link to it rather than paraphrase it. These are the anchors used for the bands above.
IHP — MPW schedule and price list, 2026
Per-area MPW prices published by technology: about €900/mm² for an interposer module, €1,300/mm² for a 130nm BEOL-only run, €4,500–€9,000/mm² across the BiCMOS and RF-CMOS families, with optional modules billed separately (for example about €12,500 per order for TSV). Minimum area on selected runs starts at about 0.8 mm².
Open source →X-FAB — MPW service terms, 2026
Registration is required at least two weeks before the published tape-in date; the released database plus documentation must be in by the data-release date; samples-out is quoted on the assumption that the most complex process variant is used.
Open source →UMC — Silicon Shuttle, 2026 shuttle plan
A marked month indicates a regular shuttle launch only if the minimum number of paid seats has been filled; otherwise UMC reserves the right to make adjustments.
Open source →GlobalFoundries — GlobalShuttle MPW programme
Marked months denote the shuttle tape-out month once minimum demand is fulfilled, and GF reserves the right to modify the plan. AMF shuttle runs require GDS by the 15th of the previous month.
Open source →GET A REAL NUMBER
From a range to a quotation
Send node range, approximate die size, package direction, volume target and preferred window. That is enough to come back with a real number for a specific run, or to tell you honestly that the range you had in mind does not fit.
RELATED
Where cost meets the rest of the plan
FAQ
Questions about cost and quotation
No. They are industry reference ranges compiled from publicly published foundry price lists, MPW programme documentation and common market practice. They are deliberately wide so they can be used to sanity-check a budget, not to place an order. The price for your programme comes from a written quotation issued after scope, node, die size and window are known.
Because the inputs genuinely differ by an order of magnitude. A 180nm shuttle seat and a 22nm shuttle seat differ by more than 10×; a small leadframe package and a 2.5D advanced package differ by more than 10×. A narrow range would be misleading, and would quickly be read as a quotation.
For prototype work it is usually the mask decision: whether you take a seat on a shared reticle (MPW) or buy a dedicated mask set. Everything else — wafer count, packaging, test — scales from there. For production work the driver becomes die size and yield, because cost per die is what multiplies by volume.
Typically around 30 days. Foundry capacity, mask blank costs, substrate and leadframe pricing, tester availability and currency all move, so a number held open indefinitely is not a number you want to plan against.
Yes. Node range, approximate die size, package direction, volume target and target window are enough to establish a realistic range. A finished GDS is only needed to reserve a shuttle seat, not to start the conversation.
CALCULATORS
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