MPW / Shuttle access

TSMC 16nm MPW

Plan a 16nm multi-project wafer run at TSMC through TOMPW Service. We coordinate shared-mask access, EDA sign-off, shuttle scheduling and the downstream packaging or test path for global chip teams.

Node: 16nmMPW, NTO and production evaluation

Why 16nm

16nm is a mature FinFET node widely used for performance ASICs with a rich IP portfolio. TOMPW coordinates 16nm MPW access and tape-out checks for first-silicon validation.

Typical applications

✓Networking and baseband
✓Automotive compute
✓Consumer SoCs

What a 16nm MPW at TSMC involves

A 16nm MPW (multi-project wafer) shuttle places several customer designs on one shared mask set, so each team pays only for its portion of the wafer. TOMPW Service handles slot selection, DRC/LVS review and logistics so your GDSII reaches TSMC's line on schedule.

Step 1
GDSII & spec
Share your GDSII, target node and tape-out window.
Step 2
Slot & mask share
TOMPW books the next shuttle and aligns mask share.
Step 3
Wafer, package, test
Wafers returned, then package/test aligned as needed.

✓MPW shuttle windows

✓NTO / engineering run support

✓Full mask production

✓Advanced node tape-out coordination

✓Package and test alignment

Platforms across TSMC

Foundry-level platforms, not a list of everything 16nm offers. Which of these apply to your 16nm run is confirmed per project.

CMOS

BCD

RF CMOS

SOI

SiGe BiCMOS

Notes on working with TSMC

Advanced node programs are evaluated case by case based on schedule and commercial model.
TOMPW helps coordinate MPW to production transition on TSMC nodes.

Best-fit applications

AI and HPC programsMobile and consumer SoCAdvanced node first-silicon validationTeams needing mature advanced-node support

Expert reviewed

This page is reviewed by Henry, CEO, TOMPW Service. Henry is the CEO of TOMPW Service and a chip-design specialist with 20 years in the semiconductor industry.

Discuss a 16nm MPW at TSMC

TOMPW Service can coordinate a 16nm MPW shuttle with TSMC as part of a scoped execution path.

Email for a Quote

COMMON QUESTIONS

Working with TSMC 16nm MPW through TOMPW

Can TOMPW arrange a 16nm MPW shuttle at TSMC?

Yes. TOMPW coordinates 16nm MPW and shuttle access at TSMC for overseas teams, handling slot selection, EDA checks and logistics so your design reaches the shared mask on schedule.

What does a 16nm MPW run at TSMC typically include?

A 16nm MPW run bundles your design onto a shared reticle with other projects, covering mask share and wafer fabrication at TSMC. Wafer-level probe is included only on the shuttles that offer it, so we confirm probe coverage for the specific run before you commit. Packaging, final test and the NTO transition are scoped separately with TOMPW.

How long does a 16nm MPW cycle take at TSMC?

Cycle time depends on TSMC's shuttle cadence for 16nm, usually a few months from mask data to returned wafers. Missing a window means waiting for the next one, so TOMPW recommends booking early.

What comes after a 16nm MPW at TSMC?

After a successful 16nm MPW, teams typically move to NTO or full-mask production. TOMPW helps plan that transition, including package selection, test development and volume ramp through TSMC and downstream partners.

PLAN & ESTIMATE