MPW / Shuttle access

SMIC 55nm MPW

Plan a 55nm multi-project wafer run at SMIC through TOMPW Service. We coordinate shared-mask access, EDA sign-off, shuttle scheduling and the downstream packaging or test path for global chip teams.

Node: 55nmMPW, NTO and production evaluation

Why 55nm

55nm is a low-cost node combining CMOS with embedded flash and BCD for value-focused designs. TOMPW coordinates 55nm MPW access for cost-sensitive programs.

Typical applications

✓MCU and embedded flash
✓PMIC and analog
✓Consumer and IoT chips

What a 55nm MPW at SMIC involves

A 55nm MPW (multi-project wafer) shuttle places several customer designs on one shared mask set, so each team pays only for its portion of the wafer. TOMPW Service handles slot selection, DRC/LVS review and logistics so your GDSII reaches SMIC's line on schedule.

✓MPW shuttle for SMIC nodes

✓NTO and production mask support

✓Mature node cost optimization

✓China-based manufacturing coordination

Technologies & platforms at 55nm

CMOS

BCD

eFlash

RF CMOS

HV CMOS

MEMS

Notes for 55nm programs

SMIC offers strong cost performance for mature and mainstream nodes.
TOMPW supports global customers accessing SMIC through a coordinated execution path.

Best-fit applications

Consumer and IoT chipsIndustrial and automotive applicationsCost-sensitive production programsTeams wanting China-based foundry access

Expert reviewed

This page is reviewed by Henry, CEO, TOMPW Service. Henry is the CEO of TOMPW Service and a chip-design specialist with 20 years in the semiconductor industry.

Discuss a 55nm MPW at SMIC

TOMPW Service can coordinate a 55nm MPW shuttle with SMIC as part of a scoped execution path.

Email for a Quote

COMMON QUESTIONS

Working with SMIC 55nm MPW through TOMPW

Can TOMPW arrange a 55nm MPW shuttle at SMIC?

Yes. TOMPW coordinates 55nm MPW and shuttle access at SMIC for overseas teams, handling slot selection, EDA checks and logistics so your design reaches the shared mask on schedule.

What does a 55nm MPW run at SMIC typically include?

A 55nm MPW run bundles your design onto a shared reticle with other projects, covering mask share, wafer fabrication at SMIC, and standard probe. Packaging, final test and NTO transition are planned separately with TOMPW.

How long does a 55nm MPW cycle take at SMIC?

Cycle time depends on SMIC's shuttle cadence for 55nm, usually a few months from mask data to returned wafers. Missing a window means waiting for the next one, so TOMPW recommends booking early.

What comes after a 55nm MPW at SMIC?

After a successful 55nm MPW, teams typically move to NTO or full-mask production. TOMPW helps plan that transition, including package selection, test development and volume ramp through SMIC and downstream partners.

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