MPW / Shuttle access
SMIC 55nm MPW
Plan a 55nm multi-project wafer run at SMIC through TOMPW Service. We coordinate shared-mask access, EDA sign-off, shuttle scheduling and the downstream packaging or test path for global chip teams.
Why 55nm
55nm is a low-cost node combining CMOS with embedded flash and BCD for value-focused designs. TOMPW coordinates 55nm MPW access for cost-sensitive programs.
Typical applications
- ✓MCU and embedded flash
- ✓PMIC and analog
- ✓Consumer and IoT chips
What a 55nm MPW at SMIC involves
A 55nm MPW (multi-project wafer) shuttle places several customer designs on one shared mask set, so each team pays only for its portion of the wafer. TOMPW Service handles slot selection, DRC/LVS review and logistics so your GDSII reaches SMIC's line on schedule.
Step 1
GDSII & spec
Share your GDSII, target node and tape-out window.
Step 2
Slot & mask share
TOMPW books the next shuttle and aligns mask share.
Step 3
Wafer, package, test
Wafers returned, then package/test aligned as needed.
Platforms across SMIC
Foundry-level platforms, not a list of everything 55nm offers. Which of these apply to your 55nm run is confirmed per project.
Notes on working with SMIC
- SMIC offers strong cost performance for mature and mainstream nodes.
- TOMPW supports global customers accessing SMIC through a coordinated execution path.
Best-fit applications
Expert reviewed
This page is reviewed by Henry, CEO, TOMPW Service. Henry is the CEO of TOMPW Service and a chip-design specialist with 20 years in the semiconductor industry.
Discuss a 55nm MPW at SMIC
TOMPW Service can coordinate a 55nm MPW shuttle with SMIC as part of a scoped execution path.
Email for a QuoteCOMMON QUESTIONS
Working with SMIC 55nm MPW through TOMPW
Can TOMPW arrange a 55nm MPW shuttle at SMIC?
Yes. TOMPW coordinates 55nm MPW and shuttle access at SMIC for overseas teams, handling slot selection, EDA checks and logistics so your design reaches the shared mask on schedule.
What does a 55nm MPW run at SMIC typically include?
A 55nm MPW run bundles your design onto a shared reticle with other projects, covering mask share and wafer fabrication at SMIC. Wafer-level probe is included only on the shuttles that offer it, so we confirm probe coverage for the specific run before you commit. Packaging, final test and the NTO transition are scoped separately with TOMPW.
How long does a 55nm MPW cycle take at SMIC?
Cycle time depends on SMIC's shuttle cadence for 55nm, usually a few months from mask data to returned wafers. Missing a window means waiting for the next one, so TOMPW recommends booking early.
What comes after a 55nm MPW at SMIC?
After a successful 55nm MPW, teams typically move to NTO or full-mask production. TOMPW helps plan that transition, including package selection, test development and volume ramp through SMIC and downstream partners.
PLAN & ESTIMATE
Calculators for your 55nm MPW
Estimate dies per wafer, split shared-mask cost and model unit economics before you commit to a shuttle slot.
Die Per Wafer Calculator
Count complete dies from Shot/Field layouts with flat or notched wafer boundaries, edge clearance and optional yield estimates.
Open tool →MPW Cost Sharing Calculator
Allocate an agreed MPW shared cost by booked block area and block count, without predicting delivered dies.
Open tool →Wafer & Unit Cost Calculator
Turn a wafer run into a per-chip cost: dies per wafer, yield, packaging and test, plus a target margin.
Open tool →Tape-out Budget Estimator
Full program model: DPW, yield, packaging, HBM, test, NRE and volume → unit cost, price and gross margin.
Open tool →RELATED FOUNDRY PROFILES
Other foundries teams compare SMIC with
RELATED SERVICES
Services that pair with a SMIC 55nm MPW
MPW / Fab Shuttle
Compare public shuttle windows across foundries, control first-silicon cost and move from tape-out planning to wafer delivery with one execution path.
Learn more →Full Mask / Production Foundry
Move validated designs into dedicated mask production with yield, volume and supply planning support.
Learn more →Semiconductor Packaging
Semiconductor packaging through external assembly and test providers, with TOMPW coordinating package selection, supplier review and assembly-to-test handoff.
Learn more →Test & Product Engineering
Connect CP, FT and reliability planning so packaged silicon is measurable, debuggable and ready for customer evaluation.
Learn more →Turnkey ASIC Solutions
Unify design support, tape-out, packaging, test, board work and delivery under one execution-facing partner.
Learn more →RELATED MPW NODES
Other 55nm and SMIC MPW access pages
Browse adjacent shuttle nodes so comparison and scheduling research stays on one program path.
SMIC other nodes
55nm at other foundries
CROSS-FOUNDRY COMPARISON
Compare 55nm across foundries
55nm MPW is offered by 6 TOMPW-supported foundries including SMIC. Use the node comparison tool to see per-foundry shuttle cadence, MPW cost-sharing and ecosystem notes side by side.