MPW / Shuttle access
Sai Micro Wafer-level packaging MPW
Plan a Wafer-level packaging multi-project wafer run at Sai Micro through TOMPW Service. We coordinate shared-mask access, EDA sign-off, shuttle scheduling and the downstream packaging or test path for global chip teams.
Why Wafer-level packaging
Wafer-level packaging is one of the process options TOMPW coordinates as a shared-mask MPW run at the partner foundry. We handle slot selection, EDA checks and logistics so your design reaches the line on schedule.
What a Wafer-level packaging MPW at Sai Micro involves
A Wafer-level packaging MPW (multi-project wafer) shuttle places several customer designs on one shared mask set, so each team pays only for its portion of the wafer. TOMPW Service handles slot selection, DRC/LVS review and logistics so your GDSII reaches Sai Micro's line on schedule.
Step 1
GDSII & spec
Share your GDSII, target node and tape-out window.
Step 2
Slot & mask share
TOMPW books the next shuttle and aligns mask share.
Step 3
Wafer, package, test
Wafers returned, then package/test aligned as needed.
Technologies & platforms at Wafer-level packaging
Notes for Wafer-level packaging programs
- Sai Micro is the China-based MEMS manufacturing arm of Sai MicroElectronics; Silex Microsystems (Sweden, already a TOMPW partner) is its subsidiary.
- MEMS engagements are process- and design-based rather than standard CMOS MPW shuttles; TOMPW can help scope a Sai Micro MEMS program.
Best-fit applications
Expert reviewed
This page is reviewed by Henry, CEO, TOMPW Service. Henry is the CEO of TOMPW Service and a chip-design specialist with 20 years in the semiconductor industry.
Discuss a Wafer-level packaging MPW at Sai Micro
TOMPW Service can coordinate a Wafer-level packaging MPW shuttle with Sai Micro as part of a scoped execution path.
Email for a QuoteCOMMON QUESTIONS
Working with Sai Micro Wafer-level packaging MPW through TOMPW
Can TOMPW arrange a Wafer-level packaging MPW shuttle at Sai Micro?
Yes. TOMPW coordinates Wafer-level packaging MPW and shuttle access at Sai Micro for overseas teams, handling slot selection, EDA checks and logistics so your design reaches the shared mask on schedule.
What does a Wafer-level packaging MPW run at Sai Micro typically include?
A Wafer-level packaging MPW run bundles your design onto a shared reticle with other projects, covering mask share, wafer fabrication at Sai Micro, and standard probe. Packaging, final test and NTO transition are planned separately with TOMPW.
How long does a Wafer-level packaging MPW cycle take at Sai Micro?
Cycle time depends on Sai Micro's shuttle cadence for Wafer-level packaging, usually a few months from mask data to returned wafers. Missing a window means waiting for the next one, so TOMPW recommends booking early.
What comes after a Wafer-level packaging MPW at Sai Micro?
After a successful Wafer-level packaging MPW, teams typically move to NTO or full-mask production. TOMPW helps plan that transition, including package selection, test development and volume ramp through Sai Micro and downstream partners.
PLAN & ESTIMATE
Calculators for your Wafer-level packaging MPW
Estimate dies per wafer, split shared-mask cost and model unit economics before you commit to a shuttle slot.
Die Per Wafer Calculator
Estimate gross and net dies per wafer from wafer size, die dimensions, scribe lanes, edge exclusion and yield models.
Open tool →MPW Cost Sharing Calculator
Split a shared MPW wafer cost across multiple designs by occupied wafer area — per-participant share and cost.
Open tool →Wafer & Unit Cost Calculator
Turn a wafer run into a per-chip cost: dies per wafer, yield, packaging and test, plus a target margin.
Open tool →Tape-out Budget Estimator
Full program model: DPW, yield, packaging, HBM, test, NRE and volume → unit cost, price and gross margin.
Open tool →RELATED FOUNDRY PROFILES
Other foundries teams compare Sai Micro with
RELATED SERVICES
Services that pair with a Sai Micro Wafer-level packaging MPW
MPW / Fab Shuttle
Compare public shuttle windows across foundries, control first-silicon cost and move from tape-out planning to wafer delivery with one execution path.
Learn more →Full Mask / Production Foundry
Move validated designs into dedicated mask production with yield, volume and supply planning support.
Learn more →Semiconductor Packaging
Plan package type, prototype assembly, inspection and qualification early so silicon delivery does not stall after wafer completion.
Learn more →Test & Product Engineering
Connect CP, FT and reliability planning so packaged silicon is measurable, debuggable and ready for customer evaluation.
Learn more →Turnkey ASIC Solutions
Unify design support, tape-out, packaging, test, board work and delivery under one execution-facing partner.
Learn more →RELATED MPW NODES
Other Wafer-level packaging and Sai Micro MPW access pages
Browse adjacent shuttle nodes so comparison and scheduling research stays on one program path.
Sai Micro other nodes
Wafer-level packaging at other foundries
CROSS-FOUNDRY COMPARISON
Compare Wafer-level packaging across foundries
Wafer-level packaging MPW is offered by 2 TOMPW-supported foundries including Sai Micro. Use the node comparison tool to see per-foundry shuttle cadence, MPW cost-sharing and ecosystem notes side by side.