MPW / Shuttle access

XMC 65nm MPW

Plan a 65nm multi-project wafer run at XMC through TOMPW Service. We coordinate shared-mask access, EDA sign-off, shuttle scheduling and the downstream packaging or test path for global chip teams.

Node: 65nmMPW, NTO and production evaluation

Why 65nm

65nm is a widely available, low-cost node with mature PDKs and ample IP. TOMPW coordinates 65nm MPW shuttles for prototype and volume production alike.

Typical applications

✓MCU and IoT chips
✓Mixed-signal and RF
✓PMIC and consumer ICs
✓Industrial applications

What a 65nm MPW at XMC involves

A 65nm MPW (multi-project wafer) shuttle places several customer designs on one shared mask set, so each team pays only for its portion of the wafer. TOMPW Service handles slot selection, DRC/LVS review and logistics so your GDSII reaches XMC's line on schedule.

✓NOR Flash process coordination

✓CIS and pixel platform support

✓MEMS integration

✓Mature-node analog production

Technologies & platforms at 65nm

NOR Flash

CIS (CMOS image sensor)

MEMS / analog

Embedded memory

Notes for 65nm programs

XMC runs mature-to-mainstream specialty platforms; shuttle availability is confirmed per program.
TOMPW can coordinate an XMC NOR / CIS / MEMS engagement.

Best-fit applications

NOR Flash and embedded memoryImage-sensor and optical devicesMEMS and sensor programsMature-node analog ICs

Expert reviewed

This page is reviewed by Henry, CEO, TOMPW Service. Henry is the CEO of TOMPW Service and a chip-design specialist with 20 years in the semiconductor industry.

Discuss a 65nm MPW at XMC

TOMPW Service can coordinate a 65nm MPW shuttle with XMC as part of a scoped execution path.

Email for a Quote

COMMON QUESTIONS

Working with XMC 65nm MPW through TOMPW

Can TOMPW arrange a 65nm MPW shuttle at XMC?

Yes. TOMPW coordinates 65nm MPW and shuttle access at XMC for overseas teams, handling slot selection, EDA checks and logistics so your design reaches the shared mask on schedule.

What does a 65nm MPW run at XMC typically include?

A 65nm MPW run bundles your design onto a shared reticle with other projects, covering mask share, wafer fabrication at XMC, and standard probe. Packaging, final test and NTO transition are planned separately with TOMPW.

How long does a 65nm MPW cycle take at XMC?

Cycle time depends on XMC's shuttle cadence for 65nm, usually a few months from mask data to returned wafers. Missing a window means waiting for the next one, so TOMPW recommends booking early.

What comes after a 65nm MPW at XMC?

After a successful 65nm MPW, teams typically move to NTO or full-mask production. TOMPW helps plan that transition, including package selection, test development and volume ramp through XMC and downstream partners.

RELATED FOUNDRY PROFILES

Other foundries teams compare XMC with

PSMC (Powerchip)MPW & access →CanSemiMPW & access →SJ SEMIMPW & access →HLMCMPW & access →

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