Knowledge Hub · Topic
Test & DFT guides
Wafer sort, final test, DFT architecture, burn-in, SLT and quality targets — what each step costs, when it is needed and what to prepare before tape-out.
Wafer Sort (CP) vs Final Test (FT): What Each One Catches
Circuit probe and final test are not redundant. Learn what wafer sort catches cheaply, what only final test can see, and how to split coverage between them.
ATE Time, Probe Cards and Load Boards: Where Test Cost Really Goes
Test cost is usually quoted as a per-hour tester rate. The real drivers are test time, tester class and the NRE of probe cards and load boards.
DFT Basics: Scan, BIST and JTAG for ASIC Teams
Design for test is decided before tape-out, not after wafer return. A plain-language guide to scan, compression, BIST and boundary scan.
Reliability Qualification: HTOL, ESD and AEC-Q100 Explained
What qualification actually proves, which stresses are standard, and when a part genuinely needs AEC-Q100 versus a lighter qualification plan.
Burn-In and System-Level Test: When They Pay For Themselves
Burn-in and SLT are expensive insertions. Learn which failure modes justify them and which programs should skip both.
DPPM Targets and Yield: Setting Test Escape Limits That Make Sense
DPPM is a business decision dressed up as a test metric. How to set a defensible target and what it costs to hit it.
Reducing Test Cost: DFT, Yield and ATE Strategy
Test cost is paid on every die, good or bad. Learn how design-for-test, yield learning and ATE strategy cut cost per good unit without shipping risk.
How to work through it
The order these decisions actually arrive in
01
Decide the DFT architecture, before tape-out
Scan, BIST and JTAG structure decide what silicon can be observed later. This is a design decision with a test bill attached, and it cannot be retrofitted cheaply.
02
Split coverage between CP and FT
Wafer sort removes bad die before packaging money is spent; final test proves the packaged part. Deciding what each insertion catches is the single biggest lever on cost per good unit.
03
Model where the test money goes
Tester minutes, load board, handler and probe card — one-time hardware against per-part seconds. The mix, not the tester rate, usually decides the number.
04
Decide whether extra insertions pay
Burn-in and system-level test catch failure modes that ATE misses. They are worth it for some products and dead money for others.
05
Set the quality target and prove it
DPPM and yield targets define how much test is enough, and qualification is the evidence a customer or an automotive programme will ask for.
Which guide answers what
Pick by question, not by title
| Question | Read | What it settles |
|---|---|---|
| Do I need both wafer sort and final test? | cp vs ft testing | What each insertion catches, and what skipping CP costs once packaging is paid for |
| Where does test cost actually go? | ate and probe card cost | Tester time, load board, probe card and handler — one-time vs per-unit |
| How much DFT is enough? | dft basics scan bist jtag | Coverage against test time, area and schedule |
| Do I need burn-in or SLT? | burn in and slt when needed | Which failure modes justify an extra insertion, and which programmes should skip it |
| What escape rate can I accept? | dppm and yield targets | Automotive against consumer DPPM targets, and what tightening them costs |
| What does qualification actually require? | reliability qualification htol esd aec q100 | HTOL, temperature cycling, ESD, latch-up and the AEC-Q100 grades |
Numbers to sanity-check against
Reference figures
Test share of chip cost
Commonly cited at 15–30%, higher for mixed-signal and RF
Automotive DPPM target
Single digits to ~50 escapes per million shipped
Consumer DPPM target
Commonly 100–200 escapes per million shipped
Scan compression
Widely used at 50–100×, turning minutes of test time into seconds
Industry-wide reference points, not quotations. Your numbers depend on node, package, volume and test coverage — model them with the tools below.
EXECUTION
How TOMPW runs it
Connect CP, FT and reliability planning so packaged silicon is measurable, debuggable and ready for customer evaluation.
Test & Product Engineeringservice →