Design for test is the set of structures you build into the chip so that a tester can see inside it. Without them, the tester only sees the pins, and diagnosis becomes guesswork.
DFT is a tape-out decision. If scan chains are not in the netlist before you release, no amount of test engineering after wafer return will add them.
Scan: Making Flip-Flops Observable
Scan stitches the sequential elements of the design into shift registers. In test mode you shift a pattern in, capture the response, and shift it out — turning a sequential problem into a combinatorial one that ATPG can solve.
The payoff is fault coverage plus diagnosability. When a part fails, scan lets you localize the failing element, which is what turns a yield problem into a fixable design or process issue.
Compression: Why Test Time Drops
Raw scan chains are long, and shifting them is slow. Scan compression adds on-chip decompressor and compactor logic so a small number of tester channels drive many internal chains.
The practical effect is large: programs that would take minutes to shift can often run in seconds, and test time is billed on every unit. Compression costs some area and some diagnosability, which is the trade-off to evaluate per design.
- Compression trades a little area for a large reduction in test time
- Higher compression ratios can reduce diagnostic resolution
- The right ratio depends on volume, tester rate and yield-learning needs
BIST: Testing Without Patterns
Built-in self-test puts the pattern generator and response checker on the die. Memory BIST is standard practice for embedded SRAM, because external patterns for large arrays are impractical.
Logic BIST exists but is less universal. It is most attractive where tester access is limited, where in-field test matters, or where safety requirements demand periodic self-check during operation.
Boundary Scan and JTAG
Boundary scan (IEEE 1149.1, commonly called JTAG) puts controllable cells on the IO pads. It is what lets you verify board interconnect, load configuration and debug a part that is already soldered down.
It is also the usual access path for on-chip debug and for programming eFuse or OTP during test. Even in designs with no board-level test requirement, keeping a JTAG port often pays for itself during bring-up.
What DFT Costs You
DFT is not free. Scan and compression add area, add routing congestion, and add constraints to place-and-route. There is also schedule cost: DFT insertion, ATPG and pattern verification are real tasks with real duration.
The comparison worth making is against the alternative. A design without DFT typically has longer test time, lower coverage, and a much slower yield ramp — costs that are paid per unit and per week, rather than once.
