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IP & licensing guides

Sourcing and licensing third-party IP: soft vs. firm vs. hard cores, royalty and licence models, the vendor landscape, ARM vs. RISC-V, and the integration pitfalls that stall tape-outs.

Process node reference chart illustrating IP and node alignment
August 31, 20268 min readTOMPW

IP Fit Planning Before Tape-Out: A Checklist for ASIC Teams

IP choice is more than a licensing problem. This checklist walks through the four IP categories to settle first, license constraints, foundry qualification and the cost of last-minute changes.

IPIP Cores
GDSII layout view of a hardened macro block
November 5, 2024↻ 20268 min readTOMPW

Soft, Firm and Hard IP: How to Choose for an ASIC Program

The same function can arrive as RTL, as a placed netlist, or as a hardened macro. Each has a different cost, risk and schedule profile.

IPASIC
Wafer close-up representing per-die royalty accounting
December 3, 2024↻ 20268 min readTOMPW

IP Licensing Models Explained: Upfront, Royalty, Subscription and Escrow

What you actually pay for an IP core, how per-die royalties behave at volume, and which contract terms decide whether a deal is good twelve months later.

IPLicensing
Floorplan view showing multiple licensed IP blocks
January 14, 2025↻ 20269 min readTOMPW

The IP Vendor Landscape: Who Sells What, and How to Shortlist

Foundry IP programmes, large EDA vendors, processor specialists and the open-source ecosystem each solve a different problem. A practical way to shortlist.

IPASIC
SoC block diagram with a processor subsystem highlighted
February 11, 2025↻ 20269 min readTOMPW

Arm vs RISC-V for an ASIC: How the Decision Actually Gets Made

The architecture debate is usually settled by software ecosystem and qualification evidence, not by the instruction set. What to weigh for a real program.

IPASIC
Timing report and clock domain diagram on a design review screen
March 18, 2025↻ 20269 min readTOMPW

IP Integration Pitfalls: CDC, UPF, Timing and the Late ECO

Most IP problems are not in the core. They are in clock domain crossing, power intent, interface timing and the ECO that arrives two weeks before tape-out.

IPASIC

How to work through it

The order these decisions actually arrive in

01

Decide what to buy, not build

Standard cells, memory, PLLs, PHYs and CPUs are almost always bought. The buy-or-build line is drawn by schedule risk, not by licence fee.

02

Choose the delivery form

Soft RTL is portable and flexible; firm netlist trades flexibility for timing certainty; hard GDSII is fastest to integrate and least portable across foundries.

03

Model the money at your volume

Upfront licence against per-die royalty, single-use against multi-use, and the support and integration effort nobody puts in the spreadsheet.

04

Shortlist by block, not by brand

Each vendor is strong somewhere specific. A shortlist is built block by block — CPU, interface, memory, analog, security — then checked against your node.

05

De-risk integration before it stalls the tape-out

Clock domain crossing, power intent, timing closure and ECO are where IP-heavy programmes actually slip.

Which guide answers what

Pick by question, not by title

QuestionReadWhat it settles
Which blocks should be licensed, not designed?ip fit planning before tape outThe checklist that prevents a late IP surprise
Soft, firm or hard?soft firm hard ip which to chooseWhat you receive, and who carries the integration risk
What will it cost at my volume?ip licensing models explainedUpfront fees, royalties, subscriptions, escrow and the break-even volume
Arm or RISC-V?arm vs riscv for asicHow the architecture decision is actually made on a real programme
Which vendor for which block?ip vendor landscapeFoundry programmes, portfolio vendors and specialists, by block type
What breaks during IP integration?ip integration pitfalls cdc upf timingCDC, power intent, timing closure and the cost of a late ECO

Numbers to sanity-check against

Reference figures

  • Portability

    Hard IP is tied to a foundry and node — re-targeting means re-characterisation

  • Licence shapes

    Upfront plus per-die royalty, single-use vs multi-use, subscription

  • Escrow

    Source escrow adds a fee and an administrative step, and is often skipped

  • Integration risk

    CDC, UPF power intent and timing closure are the usual slip points

Industry-wide reference points, not quotations. Your numbers depend on node, package, volume and test coverage — model them with the tools below.

EXECUTION

How TOMPW runs it

Third-party semiconductor IP sales and sourcing, with process-fit review, licensing coordination and clearly scoped integration support.

IP Cores & Licensingservice →