A licensed core that works in isolation tells you very little about whether it will work in your chip. The failures that cost schedule happen at the boundaries.
Four of them account for most of the pain: clock domain crossing, power intent, timing budgets across the interface, and the ECO that lands when the floorplan is already frozen.
Clock Domain Crossing (CDC)
Every signal that crosses between asynchronous clocks is a metastability risk. Cores usually document their required synchroniser structure, and the integrator is responsible for implementing it correctly on every crossing.
The failure mode is intermittent: a design can pass simulation and fail in silicon once in a thousand times. CDC-specific static checking exists for exactly this reason and should run on the integrated design, not just on individual blocks.
- Never assume a core handles CDC internally — verify per interface
- Run CDC structural checks on the assembled design
- Watch for reconvergence and for multi-bit signals crossing without grey coding or handshake
UPF and Power Intent
Power intent describes which domains exist, when they switch off, and what isolation and level shifting is required between them. If the core's UPF and your SoC's UPF disagree, you get isolation gaps and retention bugs that appear only in low-power modes.
The trap is that these bugs are invisible in a design that never exercises the power-down path. Confirm the low-power modes are actually simulated before tape-out, not just structurally checked.
Interface Timing Budgets
The core's timing model is only valid for the corners and constraints it was built against. Your clock tree, your IO delays and your operating conditions are different, and the interface budget has to be re-derived in your context.
Agreement on clock frequency, latency expectations and allowable skew should be explicit and written down during integration planning. Late discovery of a two-cycle latency assumption is a common cause of a painful ECO.
The Late ECO
An engineering change order near tape-out is normal; an unplanned one is expensive. The preventable ones usually trace back to a constraint that was assumed rather than specified.
Reserving margin — area, timing and schedule — is cheaper than any fix. A floorplan with no slack left cannot absorb a correction, and at that point the options are a mask respin or a compromised product.
A Pre-Tape-Out Checklist
The integration review worth running is short and specific. Confirm CDC checks are clean on the assembled design, UPF is consistent across all domains and simulated, interface timing is closed at all corners, and DFT is inserted and verified through the core boundaries.
If the core is hard IP, also confirm the abstract matches the delivered GDSII and that the LVS and DRC results were generated with the same rule deck revision you are signing off against.
- CDC structural and functional checks on the integrated netlist
- UPF consistency plus simulated low-power entry and exit
- Interface timing closed across all signoff corners
- DFT patterns verified through IP boundaries
- DRC and LVS run against the current foundry rule deck
