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Synopsys in FY2026 Q3: What the Numbers Say About EDA and IP Supply

What Synopsys' FY2026 Q3 results reveal about EDA and design IP availability: revenue by segment, Ansys contribution, portfolio divestitures and the export-control assumption behind the guidance.

September 25, 2026Updated September 25, 20268 min readBy Henry
IPASICTape-OutCost

EDA vendors rarely appear in a tape-out plan, but they decide what is actually buildable: which IP exists for a node, whether the flow closes, and how much verification time a programme burns.

This reads Synopsys' reported third-quarter fiscal 2026 results as supply intelligence rather than an earnings summary. Figures are the company's own reported numbers.

The Quarter in Numbers

For the third quarter of fiscal 2026, ended 31 July 2026 and reported on 26 August 2026, Synopsys reported revenue of USD 2.477 billion, against USD 1.740 billion in the same quarter a year earlier — growth of roughly 42 per cent.

The two reported segments moved very differently. Design Automation, which now includes Ansys products alongside EDA, verification and manufacturing software, contributed USD 2.003 billion against USD 1.312 billion. Design IP contributed USD 473.8 million against USD 427.6 million, about 11 per cent growth, returning to year-on-year growth after a softer period.

GAAP net income was USD 545.8 million, or USD 2.84 per diluted share. On a non-GAAP basis net income was USD 752.5 million, or USD 3.91 per diluted share, with a non-GAAP operating margin of 41.6 per cent.

The Ansys Effect

The Ansys acquisition closed about a year before this quarter, at roughly USD 14.3 billion. Ansys contributed USD 711 million of revenue in the quarter and is expected to contribute roughly USD 2.98 billion across fiscal 2026. Total debt was reported reduced to USD 10 billion through early term-loan repayment, with cost synergies targeted at USD 400 million by the fourth year after close.

The commercially relevant milestone is product, not revenue: the first joint Synopsys and Ansys offering, Multiphysics Fusion, launched this quarter, with customer results cited around ten times faster design closure. For packaging-heavy programmes this matters, because chip, package and board thermal and mechanical behaviour have traditionally been analysed in separate tools with separate models.

What It Signals for IP Availability

Design IP returning to growth was explicitly called out by management. Reported detail included around a 95 per cent win rate on PCIe 7.0 opportunities and roughly 90 per cent automotive design win rates across three consecutive quarters, plus use of the 3DIC Compiler on advanced packaging programmes including AMD's Instinct MI455X GPU.

Read carefully, though: the portfolio is also being trimmed. Reported divestitures include the Optical Solutions Group and PowerArtist RTL businesses, around USD 110 million, and the Processor IP Solutions business, about USD 40 million. A divested product line is a product line with an uncertain roadmap, and that is worth confirming before building a design around it.

  • Interface and memory IP tied to AI infrastructure is where reported demand concentrated.
  • Processor IP was divested — confirm roadmap and support for any block you plan to depend on.
  • Advanced packaging tool flows are converging with chip flows; expect package analysis earlier in the schedule.

The Caveat Inside the Guidance

Full-year fiscal 2026 revenue guidance was raised to USD 9.690–9.740 billion, with non-GAAP EPS of USD 15.04–15.10. Reported free cash flow for the quarter was USD 746 million, with USD 3.6 billion cash and backlog of USD 10.9 billion.

One line deserves attention from any team sourcing tools or IP into China: the company stated that its targets assume no further changes to export control restrictions or to current US Entity List restrictions. That is a stated assumption, not a prediction, and it is the single biggest external variable in EDA and IP supply.

How to Use This

For a design team the practical takeaway is about planning horizon, not vendor selection. EDA and IP availability for a given node is a moving target shaped by portfolio decisions and by regulation, so the useful discipline is to confirm availability for your specific process version at the point you commit, rather than relying on a general platform name.

  • Confirm each block against the exact PDK and library release you will tape out on.
  • Ask about roadmap status for any product line that has recently changed hands.
  • Keep the export-control assumption explicit in your own schedule risk register.

Article FAQ

Quick answers tied to this topic

Indirectly but materially. Portfolio decisions visible in the results — what is growing, what is divested, where development resource is going — determine which IP and flow support exists for your node two to three years out. Confirming block availability for your specific process version is always the buyer's verification step.

Because it is the vendor stating, in its own filing, that its outlook depends on no further tightening of export controls or Entity List restrictions. Any programme sourcing EDA tools or IP into China carries that as an external schedule risk. It should sit in your risk register rather than being assumed away.

Not automatically. A divestiture means the product moves to a different owner with a different roadmap and support commitment. If a block is central to your design, confirm in writing what support continues, for how long, and on which process versions before you commit the architecture.

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