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Soft, Firm and Hard IP: How to Choose for an ASIC Program

Compare soft, firm and hard IP for ASIC design: what you actually receive, how each affects timing closure, portability, NRE and schedule, and which one fits which program.

November 5, 2024Updated September 18, 20268 min readBy Henry
IPASICTape-OutPhysical DesignCost

Asking for 'the IP' is not specific enough to price. Vendors deliver the same function in different forms, and the form determines who carries the integration risk.

Three broad categories cover most of the market: soft, firm and hard. The differences show up in cost, schedule, portability and in how much work is left after you sign.

Soft IP: Source You Integrate Yourself

Soft IP usually arrives as synthesizable RTL, plus a verification environment and documentation. You run synthesis, place and route, and timing closure yourself.

The advantage is portability: the same core can target multiple foundries and nodes. The cost is that integration risk sits with you, and timing, area and power are not known until you finish the build.

  • Portable across foundries and nodes
  • You own synthesis, floorplanning and timing closure
  • Performance is not guaranteed until your build is complete

Firm IP: Partially Committed

Firm IP sits between the two: typically a netlist with some placement or structural commitment, but not a final hard macro. It reduces part of the integration work while retaining some flexibility.

In practice firm IP is less commonly offered than soft or hard, and the exact deliverable varies by vendor. Ask specifically what artefacts you receive before comparing quotes.

Hard IP: A Hardened Macro

Hard IP arrives as a validated layout — usually GDSII plus a timing model, a power model and an abstract for place and route. The vendor has already closed timing and often has silicon proof at the target node.

This is the normal form for analog blocks, memory compilers and high-speed interface PHYs, where the layout is the design. It removes a large amount of risk and a large amount of schedule, in exchange for being tied to a specific foundry and node.

  • Timing, area and power are characterised for that node and library, and usually committed by the vendor for it
  • Locked to a specific foundry, node and sometimes a specific process variant
  • Floorplan and IO ring constraints are fixed and non-negotiable

What the Choice Does to Risk

Soft IP moves timing closure, DFT insertion, and physical integration onto your schedule and your team. Hard IP moves most of that to the vendor, but then constrains your floorplan and reduces your freedom to change the process later.

The practical question is not which is better, it is which risk you are better equipped to carry: integration risk that you control, or dependency risk that you do not.

Node and Volume Change the Answer

On mature nodes with a long history, soft RTL is often good enough and much cheaper. On advanced nodes, or for anything analog or mixed-signal, hard IP is frequently the only realistic option.

Volume matters for the commercial side. A per-die royalty on a soft core may be cheaper at prototype volume and more expensive at production volume than a hard macro with a higher upfront fee — which is the trade the licensing model has to make explicit.

Article FAQ

Quick answers tied to this topic

Not always, but it is often the safer choice for analog, memory and PHY functions where layout quality dominates the result. For pure digital logic at moderate performance targets, soft RTL can be entirely adequate and considerably cheaper.

Generally no, not without re-hardening. A hard macro is qualified against one process design kit. If multi-foundry optionality matters to your program, say so before you license, because it affects whether soft IP is the better commercial choice.

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