This is a real sourcing inquiry, not a template. It covered seven line items: 6-inch prime-grade silicon at two thicknesses, 6-inch test-grade, 4-inch prime, 6-inch SOI, and 6-inch and 4-inch borosilicate glass. Supplier names and prices are withheld; the specification content is reported as written.
The value of looking at a real one is that every line in it exists for a reason, and the lines people omit are the ones that generate a second round of questions from the supplier.
Prime versus test grade: the surface limits
Both grades in this inquiry were CZ-grown, N-type phosphorus-doped, <100> ±0.5°, 1–10 Ω·cm, double-side polished with two SEMI standard flats. The difference is entirely in the surface limits:
- Prime grade: TTV < 5 µm, BOW < 30 µm, WARP < 40 µm, surface roughness Ra < 1 nm
- Test grade: TTV < 10 µm, same BOW and WARP limits, same thickness tolerance
- Both: thickness 675 µm ± 20 µm on the 6-inch 675 µm item; ± 40 µm on the test-grade variant
The SOI stack
The SOI item was specified for pressure sensor fabrication, and the three thicknesses are the whole specification:
- Device silicon: 30 ± 0.5 µm, N-type <100>, resistivity 1–10 Ω·cm
- Buried oxide: 1 ± 0.1 µm
- Handle silicon: 400 ± 8 µm
- Double-side polished, surface roughness < 1 nm
Why the device layer tolerance is the tight one
Half a micron on thirty. That tolerance is what determines how repeatable the sensor's diaphragm thickness is, and therefore how tightly the device performance can be specified. A supplier who cannot hold ±0.5 µm on the device layer is not a substitute supplier for this part, whatever their price on the handle wafer.
Borosilicate glass
The glass items were specified as borosilicate, 1000 ± 20 µm thick, double-side polished, Ra < 5 nm, with a protective chamfer on the edge and two half-standard flats for alignment. The chamfer and the flats are easy to omit and both generate a follow-up question if left out: the chamfer affects handling in cassettes, and the number and orientation of flats affects how the wafer seats in downstream fixtures.
Why SOI has to be specified as a separate part
SOI is not a silicon wafer with an option box ticked. It is made by bonding a handle wafer to a device wafer with an oxide layer between, then grinding and etching the device side back to thickness. That is a separate manufacturing chain, which is why it behaves differently from the other six line items in the inquiry.
The practical consequence is that it cannot be substituted on price. A supplier quoting silicon competitively is not automatically quoting SOI competitively, and the device-layer tolerance is the parameter where that shows up first.
Commercial structure worth knowing in advance
The quote carried a 30-day validity, 13% VAT invoicing and 100% prepayment. None of those are unusual for small-volume substrate orders, and all three are easier to accept before they are read for the first time on a quote that is already against a deadline. Asking about validity and payment terms at inquiry stage, alongside the technical questions, costs nothing.
Outcome
The seven line items were specified, quoted and delivered against the requirements above. The specification described here is the one the supplier quoted from — there was no second clarification round — and the material delivered met the customer's requirements.
