This is a real requirement, not a hypothetical. A team arrived with a working asynchronous 6T SRAM they had designed themselves on 130 nm in Cadence Virtuoso — a 32 × 32 array with precharge, row decoder, read/write circuitry, sense amplifiers and a controller, no external clock for read or write — and needed 16 Mb on SMIC 40LL.
Their own assessment of the gap was accurate and worth quoting: scaling up from the 1 Kb block would give large area and power, and timing would be worse. They had already compared their own PPA against a memory compiler output and knew the compiler won. The question was what to do about it.
What the 1 Kb block actually measured
The measured numbers matter because they are the honest baseline any scale-up has to start from:
- 6T bit cell area: 14.1 µm²
- 32 × 32 array area: 0.0187 mm²
- Complete 1 Kb block area: 0.0638 mm²
- Post-layout read access: 6 ns
- Post-layout write access: 4 ns
- Power consumption: 850 µW
What the periphery costs you
The gap between the array (0.0187 mm²) and the block (0.0638 mm²) is the periphery — decoder, sense amps, control, routing. At 1 Kb that is 71% of the block. In a compiler-generated memory the periphery is amortised far better, which is the whole reason compiler output wins on PPA at scale.
The target specification
The 16 Mb target was specified as: 16 Mb capacity, asynchronous parallel host interface, 16-bit word, access time under 20 ns, −40 °C to +125 °C operating range, 0.9 V data retention voltage, independent upper and lower byte control, no external clock, on SMIC 40LL at 1.1 V with 1 W power.
Two of those are the hard ones. Sub-20 ns asynchronous access at 40 nm is achievable but not automatic — it depends on sense amplifier design and on how the address path is buffered across a large array. And 0.9 V data retention means the cell has to hold state well below the nominal core voltage, which constrains the cell ratio and the write margin.
Why linear scale-up fails
Scaling the 1 Kb block to 16 Mb means roughly 16,000 times the array. Three things break on the way:
Area: the periphery does not scale, so the block-level efficiency gets worse, not better, unless the periphery is redesigned. A compiler-generated block shares sense amps and decoders across a much larger array.
Power: charge on long bitlines dominates at this size. Segmented bitlines, local sense amplifiers and distributed array organisation are standard at this capacity for a reason.
Timing: decoder delay and sense amplifier margin do not scale with the cell. A 6 ns read on 1 Kb says very little about read access on a 16 Mb array with the same cell.
The yield risk, stated plainly
A large SRAM array has a real production yield problem, and it is worth saying that plainly rather than treating it as a footnote. At this capacity the bit cell usually has to be custom rather than a generic library cell, and the array needs redundancy — spare rows and columns and the fusing to repair them. That means a custom cell designed and characterised, a redundancy scheme, and a test flow that can actually find and repair the faults.
The realistic consequence is two tape-outs: one to prove the cell and the array organisation, a second to prove the repair and the production flow. A program that plans one tape-out for a 16 Mb custom SRAM is planning to be surprised.
What the training covered
Alongside the IP, the program included a structured design training track, which is often the part that outlasts the project. The syllabus ran from digital design methodology through memory cell design, array and precharge, sensing schemes, write path, row decoder, address and clock buffering and control circuitry; then advanced material on near-threshold SRAM design, read static and write noise margin improvement, large-size cell design, multi-level word control, local sense amplifiers and distributed SRAM, segmented bitlines, segmented and auxiliary decoders and critical path timing; with lab work on Synopsys SRAM Compiler, Cadence Virtuoso schematic and layout, and Calibre SRAM physical verification.
Outcome
The 16 Mb specification was met: asynchronous parallel interface, 16-bit word, sub-20 ns access, the full −40 °C to +125 °C range and 0.9 V data retention on the target process. The implementation proposal and the training programme were delivered against the stated requirement, with the two-tape-out plan stated up front rather than discovered mid-programme.
