GLOSSARY
Semiconductor, Packaging & Test Glossary
Plain-language definitions for the terms that come up when planning MPW, packaging and test. Each term links to a deeper guide or tool where one exists.
MPW & Tape-Out
- MPW (Multi-Project Wafer)
- A wafer run where multiple customer designs share one mask set, splitting non-recurring cost. The standard low-risk path to first silicon.
- Shuttle / Fab Shuttle
- A scheduled MPW run window offered by a foundry. Designs must meet the cut-off to share that slot; missing it means waiting for the next window.
- NTO (New Tape-Out)
- A dedicated reticle run used as a pilot or bridge before full production, when the design is close but not yet proven at scale.
- Reticle
- The patterned plate that carries one or more die images; the mask set is stepped across the wafer to print each die.
- Full Mask
- A dedicated reticle set bought for volume production. Unlike MPW, one customer owns the whole mask, so cost is higher but capacity is reserved.
- Tape-Out
- Releasing final GDSII and mask data to the foundry to start fabrication. A tape-out can be an MPW share, an NTO or a full-mask run.
- Wafer Lot / Start
- A batch of wafers processed together through the line. Lots are the unit of scheduling and yield tracking at the foundry.
- NRE (Non-Recurring Engineering)
- The one-time cost of masks, design and setup before volume units exist. MPW spreads NRE across many customer designs.
Wafer, Die & Process
- Wafer
- A thin slice of semiconductor material (typically silicon) on which many identical dies are fabricated in parallel.
- Die
- A single functional chip on a wafer before it is singulated, packaged and tested. Net good dies per wafer drive unit cost.
- Yield
- The fraction of fabricated dies that function correctly. Test yield determines how many good units you get from the parts you pay to test.
- Foundry
- A factory that fabricates wafers to a customer's design. TOMPW works across TSMC, UMC, SMIC, GlobalFoundries, Tower and more.
- Process Node
- The minimum feature size of a process (e.g. 28nm, 5nm). Smaller nodes pack more transistors but cost more and change the MPW window.
- CMOS / BCD / BiCMOS / FinFET
- Process technologies: CMOS for logic, BCD for smart power, BiCMOS for high-speed analog, FinFET for advanced-node 3D transistors.
- FD-SOI
- A planar CMOS variant with a thin buried oxide for low-power, RF-friendly chips — a GlobalFoundries specialty platform.
- SiGe BiCMOS
- A process adding silicon-germanium bipolar devices to CMOS for high-speed RF and mmWave. Offered by Tower, GF, X-FAB and others.
- GaN / GaAs / SiC (Compound Semiconductors)
- GaN and GaAs for RF, power and optoelectronics; SiC for high-voltage power. Supported by AWSC, Sanan, Dynax and ST.
- MEMS
- Micro-electro-mechanical structures built on silicon for sensors and actuators. Supported by Tower, SMIC, Silex and SJ-SEMI.
- Silicon Photonics
- Integrating optical waveguides with CMOS for high-speed data links. Offered by Tower, GF and selected fabs.
Packaging & Assembly
- OSAT
- Outsourced Semiconductor Assembly and Test — a specialist house that packages, assembles and tests wafers into finished parts.
- Wire Bond
- Connecting die bond pads to the package with thin wires. Low cost, but wire inductance limits high-frequency and high-current use.
- Flip-Chip
- Face-down die attach through solder bumps for the shortest, lowest-parasitic path. Best for RF, high speed and high thermal loads.
- QFN / BGA / WLCSP / SiP
- Package families: QFN (leadless, exposed pad), BGA (ball grid), WLCSP (wafer-level, smallest), SiP (multiple dies integrated).
- TSV / 2.5D / 3D (Chiplet)
- Through-silicon vias enable die stacking: 2.5D places dies on an interposer, 3D stacks them for chiplet-style integration.
- Fan-Out / InFO
- Wafer-level packaging that spreads I/Os beyond the die for short interconnect and thin form factor. Popular for mobile and RF.
- Underfill / Encapsulant
- Epoxy filled under a flip-chip die to protect joints from stress and thermal cycling — a key reliability step after attach.
- KGD (Known Good Die)
- Dies fully tested before packaging so only verified parts enter assembly. Driven by chip-probe at the foundry.
Test & Yield
- DFT (Design for Test)
- Design techniques — scan chains, BIST, boundary scan — that make faults observable, cutting test time and speeding yield learning.
- ATE (Automatic Test Equipment)
- The tester that applies stimulus and measures response on every device. Its hourly rate and test time drive per-device test cost.
- CP (Chip Probe) / FT (Final Test)
- CP (wafer sort) tests dies on the wafer; FT tests the packaged part. Together they catch failures before customer shipment.
- Yield Learning / Binning
- Sorting tested devices into performance bins to maximise shipped value, and using fails to improve the next lot.
- Burn-In
- Stressing parts at elevated temperature and voltage to weed out early-life failures before shipment. Common for automotive and industrial.
- Boundary Scan / JTAG
- A DFT standard for testing board-level interconnect through a shift register, complementing on-die scan chains.
Commercial
- Turnkey
- A single-vendor model that owns the program from specification to delivered, tested parts — reducing handoff risk for the buyer.
- IP Core
- A reusable, pre-verified block (SerDes, PLL, ADC, memory compiler) licensed into a design to save time and risk.
- Shuttle Slot / Cut-off Date
- The reservation window and its closing date for a given MPW run. Book before cut-off to secure the slot; miss it and wait for the next.
- Mask Set
- The full set of reticles needed to print a design. MPW reuses a shared mask set; full mask buys a dedicated one.
EXPLORE MORE
Tools and guides that use these terms