Most coverage of ISSCC is numbers: submissions, acceptance rates, record sessions. What the numbers do not show is what the conference physically is — a plenary hall that fills with thousands of engineers, parallel session rooms, a student preview that runs on different rules from the main programme, and an exhibition floor whose booth composition is itself a read on where the industry is spending.
This page is a photo walk through the last four editions, 2023 through 2026. Captions describe what each scene shows and nothing more — no endorsement and no affiliation is implied with the conference, its organisers or any vendor visible in a photograph. Photographs are licensed for use on this site; please ask before reusing them.
Why the Scenes Matter
The physical composition of ISSCC tells a sourcing story that the paper list does not. A programme of 37 sessions with roughly 2,850 paid attendees in 2026 means the audience is dominated by working engineers evaluating directions, not by a trade-show crowd collecting giveaways.
The exhibition floor tells the other half: which foundries, EDA vendors, IP suppliers and research institutes consider this audience worth a booth. Reading the two together — programme plus floor — is closer to how an experienced attendee actually uses the week.
ISSCC 2026: The Opening
The 73rd ISSCC opened 15 February 2026 at the San Francisco Marriott Marquis. The welcome screen in the main hall set the tone for the week: the conference identity carries more weight inside this community than almost any other semiconductor event, and the first morning queue is part of that ritual.
ISSCC 2026: The Plenary Stage
The 2026 plenary lineup was MediaTek, IBM Research, Cadence and Apple. The opening keynote set the frame for the whole conference: AI as an end-to-end system problem, from edge inference to agentic workloads, told from a company that ships the silicon for both.
For a team planning silicon, the useful takeaway from a plenary is not the roadmap slides — it is which problems a shipping company considers important enough to put on this stage.
ISSCC 2026: EDA on the Plenary Stage
The second scene from the 2026 plenary stage: "Powering the AI Supercycle — Design for AI and AI for design". The title alone is the thesis of the current cycle: AI workloads are driving design demand, and AI is in turn being pushed back into the design flow itself.
When the largest EDA vendors take a circuits-conference stage rather than a trade-show one, they are signalling to circuit designers, not to tool buyers. That distinction matters when you read the announcement.
ISSCC 2026: Awards on the Main Stage
ISSCC opens with the field's honours as well as its keynotes. The 2026 ceremony included the IEEE Donald O. Pederson Award in Solid-State Circuits — the society's highest honour — presented on the main stage before the technical programme begins.
The award roll is worth tracking separately from the papers: it is a decade-lagged map of which contributions the field itself considers foundational.
ISSCC 2026: Keynotes as Industry Statements
Plenary backdrops are chosen as carefully as the words. A keynote staged against large-scale compute hardware rather than a process roadmap says where the speaker believes the value has moved: into systems, packaging and the hardware that carries AI workloads.
Read against the 2026 programme — where AI, compute and accelerator sessions alone carry five of the 37 paper sessions — the stage and the programme are telling the same story.
ISSCC 2026: The Student Research Preview
SRP runs on different rules from the main sessions: short oral presentations of work-in-progress student designs, with an explicit rule set on what counts as publication. The session slide states it plainly — an SRP presentation is not considered prepublication for future ISSCC or SSCS submissions, presenters must not post the presentation online, and technical details are not to be discussed with the press.
For a team recruiting or scouting, SRP is the densest room at the conference: it is where the next two years of the programme are previewing.
ISSCC 2025: The Scale of the Room
The 2025 edition filled the same format: a highlights session in the main hall with the room at capacity. Scale is the reason the conference can act as a synchronisation point for the field — when something appears on this stage, most of the circuit-design community hears it in the same week.
ISSCC 2025: Inside the Sessions
Away from the plenary hall the conference becomes a rotation of parallel session rooms. This is where the real technical work happens: 25-minute talks, floor microphones, and an audience that asks the questions reviewers would.
ISSCC 2025: How the Conference Is Covered
Sessions are covered under conference rules — camera positions at the front are part of the normal furniture of a plenary room, and the on-screen material itself is copyrighted by the presenters. The photography policy matters to anyone attending: attendee images may be used by IEEE for its own purposes, slide photos are for personal use only, and recording is not allowed without written permission.
That policy is also why original photography, used with permission and described factually, is the only clean way to show a conference like this on a company site.
ISSCC 2025: What the Plenaries Talk About
The 2025 plenary content tracked the same currents visible a year later in the paper programme: software-defined vehicles and zonal E/E architectures, AI compute, and the power delivery that both of them push into the silicon.
Automotive is a useful example — when a circuit conference gives a plenary slot to vehicle E/E architecture, the message to analog and mixed-signal teams is about where design wins will be sourced for the next decade.
ISSCC 2024: The Plenary Stage
The 2024 plenary slot shown here was titled "Fueling Semiconductor Innovation and Entrepreneurship in the Next Decade", delivered by Lip-Bu Tan — then chairman of Walden International and senior advisor and former CEO of Cadence, as the session slide reads. Within a year he was running Intel.
That trajectory is the point of a plenary: the people ISSCC invites to this stage tend to be the ones the industry hands larger jobs to, and the themes they choose — in this case where the next decade of semiconductor value gets created — age better than any single roadmap slide.
ISSCC 2024: The Pederson Award
The 2024 ceremony presented the IEEE Donald O. Pederson Award in Solid-State Circuits to Deog-Kyoon Jeong, cited on screen for leadership in the development of digital display drivers and DRAM interfaces.
Read the award roll across the years covered on this page and a pattern appears: display drivers and DRAM interfaces in 2024, low-energy signal processing in 2026. The Pederson citations are effectively a decade-lagged index of which circuit contributions the field now considers unavoidable.
ISSCC 2024: Demonstrations and the Floor
Outside the plenary hall, the demonstration sessions are where papers become physical: poster boards, live measurement setups on side tables, and authors answering questions one metre from the hardware. The posed certificate photo is part of the culture — recognition at ISSCC is handed out in rooms this size, not just on the main stage.
ISSCC 2023: Inside a Technical Session
A session room looks like this for most of the week: a single speaker, a dense slide, and an audience of specialists. The talk shown is a proposed SoC platform built around an embedded FPGA fabric — resource allocation, reconfiguration latency and the intra/inter-FPGA split on the slide.
This is the granularity at which ISSCC is actually consumed: one room, one problem class, twenty-five minutes.
ISSCC 2023: Recognising the Presenters
The conference also awards the people who explain well, not only those who design well — the 2023 Forum Presenter Award went to a doctoral candidate for a forum talk on overcoming Amdahl's law with tightly-coupled heterogeneous accelerators.
Two things are notable in that single slide: forums get their own award track, and the heterogeneous-acceleration debate was already mainstream on this stage in 2023 — two years before it dominated the paper sessions.
The Exhibition Floor: Foundries and the Ecosystem
The expo floor is small by trade-show standards and dense by every other measure. The booths map the delivery chain: foundries and their ecosystem programmes, packaging and test providers, and the IP suppliers whose blocks end up inside the chips being presented two aisles away.
The Exhibition Floor: EDA and IP
EDA and IP vendors take the largest share of the floor, usually with working demo stations rather than slide screens — emulation hooked to real boards, prototype flows running live. For a visitor, the floor is the one place in the year where the whole tool and IP chain can be walked in an afternoon.
The Exhibition Floor: Research Institutes and IDMs
The third group on the floor — research institutes, IDMs and the EDA-adjacent simulation vendors — completes the map. Their presence marks ISSCC's peculiar position: a conference where academia, IDMs, foundries, EDA and the supplier base all send the same audience in one week.
That is also why the conference is worth reading as a whole rather than as a paper list: the programme tells you what is being demonstrated, and the floor tells you who is already selling around it.
