Imagination has spent more than thirty years on GPU architecture and reports its IP inside more than twelve billion shipped devices. The E-Series is the current generation and the one that matters for anyone licensing graphics or edge AI acceleration now.
This article documents what has been published about the architecture and performance, and separates the confirmed specification from the reported strategy.
The Architectural Bet
E-Series embeds matrix multiplication directly inside the GPU core, placed next to the existing graphics arithmetic units. The stated rationale is reuse: AI workloads inherit the GPU's registers, control logic, cache hierarchy, firmware, drivers, toolchain and ecosystem rather than requiring a separate accelerator with its own software path.
The design integrates Imagination's own high-performance RISC-V firmware processor to schedule graphics and compute work in parallel. At the virtualisation layer it supports up to four cores and sixteen virtual machines, with quality of service, workload prioritisation and memory isolation — capabilities aimed at cloud gaming, cloud desktop, multi-domain automotive systems and edge platforms needing isolated secure environments.
Scalability is one to four cores, with a 40-bit address space, up to 1 TB addressable memory and peak memory bandwidth of 768 GB/s. Memory attaches over AXI to HBM, LPDDR, GDDR or unified memory.
Published Performance
At 1 GHz, a single core is specified at about 2 TFLOPS FP32. With matrix acceleration, that becomes 16 TFLOPS FP16/BF16 and 32 TOPS INT8/FP8 per core. A four-core configuration is specified above 100 TFLOPS FP16/BF16 and above 200 TFLOPS INT8/FP8, described as more than four times the previous D-Series.
On LLM inference, prefill performance is reported up to 4.7 times the previous generation. A cited example: a four-core E-Series at 1.5 GHz running a Qwen 3.5 4B class model at 0.2 seconds to first token and 150 tokens per second decode. Further cited cases include in-vehicle journey planning at roughly 0.2 seconds to first token and 150 tokens per second, and assistive glasses describing surroundings at about 0.25 seconds and 153 tokens per second.
Treat these as vendor-published figures achieved under stated conditions. They are useful for comparing generations within one vendor's roadmap, not as guarantees for a specific integration.
Precision Formats and Software
E-Series is stated as the first to bring BF16, MXFP8 and MXFP4 to the embedded domain, exposed through the industry-standard SPIR-V cooperative matrix extensions for OpenCL. The accompanying Matrix Accelerator is specified at up to 32 TOPS INT8 per core, integrated inside the shading cluster, with support for low-precision formats including FP8 and MXFP4.
Software support is stated as DirectX 12, OpenCL and Vulkan across Linux, Android and Windows, with ONNX and PyTorch support and upstreaming work for llama.cpp. Neural Super Resolution, an AI upscaling feature, is specified at 540p to 1080p in 2.3 ms with about half the memory bandwidth of the conventional path. A shorter pipeline introduced with E-Series, described as Burst Processors, is credited with up to 39 per cent power efficiency improvement.
The Strategy Behind the Product
Technology press reporting, citing interviews, describes Imagination narrowing its portfolio: discontinuing the RISC-V CPU line launched in 2021 and shelving an NPU designed before transformer workloads dominated, to concentrate engineering on a unified GPU architecture. A USD 100 million loan taken two years earlier is reported as funding a next-generation F-Series targeting everything from automotive to data centre, with two customers reported signed.
This is secondary reporting rather than a company filing, and it is recorded here as such. The internal RISC-V firmware processor inside E-Series is a separate matter from the discontinued RISC-V CPU product line, and the two should not be conflated.
What is directly verifiable from the company: leadership change with Markus Mosen appointed chief executive, GPU IP made available through the SiFive RISC-V design platform, functionally safe GPU IP contributed to the CHASSIS automotive base die programme, and a DXTP graphics generation.
What to Verify Before Licensing
GPU IP is unusually dependent on integration context, so the usual verification list applies with more force here.
- Which process node, library version and PDK release is the core characterised and available for?
- Are the published throughput figures specified at your target frequency, or only at the vendor's reference point?
- Is the safety coverage level you need — ASIL-B is cited — available on the configuration you are licensing?
- What is the driver and toolchain support commitment for your operating system and product lifetime?
- Are the AI frameworks you depend on supported on the generation you are actually buying?
