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Foundry Process Updates in 2026: What Changed, and What It Does to Node Choice

What 2026 foundry capacity and technology movements mean for teams choosing a node: BCD and power availability, the advanced packaging pull, and the questions to settle before locking a process.

September 25, 2026Updated September 25, 20268 min readBy Henry
Process NodeFoundryMPWCostTape-Out

Node choice is usually presented as a performance-versus-cost curve. In 2026 the more useful frame is availability: which processes actually have running capacity, shuttle cadence and downstream assembly support behind them.

This piece summarises what is publicly verifiable about 2026 foundry movement and converts it into the questions that decide a node for a real programme.

What Happened in the First Three Quarters of 2026

SEMICON China 2026 ran in Shanghai from 25 to 27 March 2026 and drew more than 1,500 exhibiting companies and over 180,000 professional visitors, with around 40 Shanghai STAR Market semiconductor companies exhibiting collectively. The STAR Market now hosts 128 listed semiconductor companies, covering design, manufacturing, equipment and materials.

On the capacity side, SMIC was reported adding roughly 50,000 twelve-inch wafers per month of capacity annually, with 2025 capital expenditure held at around USD 7.5 billion. Reported alongside that was the 29 January 2026 unveiling of the SMIC Advanced Packaging Research Institute, targeting thermal management, yield control and EDA co-optimisation.

The pattern across those two facts is the useful part: capacity expansion and packaging capability build-out are being run together, not sequentially. A team choosing a node today is choosing into a supply chain where wafer supply and advanced assembly are being planned jointly.

The Three Named Trends, Translated

SEMI China framed 2026 around AI compute, the memory cycle, and upgrade driven by advanced packaging. Translated into what a small design team should do differently: the programmes consuming the most leading capacity are compute and memory, which means mainstream logic nodes are where competition for space is mildest and shuttle cadence is most predictable.

That is a genuine advantage for industrial, automotive-adjacent and mixed-signal teams. Mainstream nodes are not exciting, and in 2026 that is precisely the point.

BCD and Power: The Quietly Busiest Front

The CSTIC 2026 programme, held 22–24 March 2026 in Shanghai, carried a plenary talk on advanced power technology for a green future from HHGrace, alongside Yangtze Memory on its Xtacking architecture. The presence of power technology in a plenary slot is a reasonable signal for where process development energy is going.

For BCD specifically, the practical consequence is that mature BCD nodes remain widely available and comparatively price-stable while leading logic capacity is tight. A power management or mixed-signal analogue programme generally has more node options than requirements.

  • Do not assume a more advanced node is more available — the reverse is often true.
  • For analogue-heavy designs, check whether the specialty platform already exists rather than porting to a logic node.
  • Confirm high-voltage and isolation options against the specific process version, not the platform name.

Memory and Integration Pull Programmes Sideways

Storage was named as one of the three 2026 forces, and heterogeneous integration appears as a standing symposium topic at CSTIC 2026. The combined effect on ordinary teams is subtle: architectures that used to sit in one die are being split, and each split die then has a package problem.

If your programme is considering splitting a design for yield or cost reasons, the node choice becomes two node choices plus an interconnection choice. Sometimes that is the right call. It is never the simpler call.

Questions to Settle Before Locking a Node

Most node decisions get made on incomplete information because the right questions were not asked in the first week. The list below is short enough to actually use.

  • Which shuttle windows actually exist for this node in the quarters you care about, and is the cut-off date a hard date?
  • Is the IP you need available for this process version, or only for the one it replaced?
  • Does your package route have Capacity for this die size, or are you specifying something only one line can build?
  • What is the realistic path from this MPW result to a full-mask conversion at your target volume?
  • If the answer to any of these is unclear, what is the fallback node?

Article FAQ

Quick answers tied to this topic

Harder for programmes competing with AI compute and memory demand, because that is where leading capacity is being absorbed. Mainstream and specialty nodes are comparatively accessible, which is why most MPW programmes sit there comfortably and should not feel pressure to move down-node without a performance reason.

Ask which one is genuinely constrained. If your design depends on a specific transceiver or processor core, the node is decided by where that core is qualified. If your design is ordinary logic and standard interfaces, choose the node on cost, availability and shuttle cadence, then source IP for it. Choosing IP first and discovering it is not qualified for your preferred process is the expensive version of this mistake.

Not automatically. New capacity is usually committed to high-volume customers before it is available to the open market, and MPW runs depend on shuttle cadence rather than total capacity. What expansion improves over time is breadth of available platforms, not necessarily your specific slot.

Compare it against the cost of achieving the same function on a general-purpose logic node, including area penalty, IP availability and qualification risk. BCD usually wins when you need high voltage, precision analogue or power integration on one die. It loses when the analogue content is small enough that a standard node plus external parts is simpler.

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