Case Study: The Library and PDK Gaps Found Before a SMIC 40LL Tape-Out

A real SMIC 40LL tape-out preparation surfaced three library and PDK gaps — no QRC extraction techfile, MOM-only capacitors where MIM was needed, and unconfirmed PLL terms. A pre-tape-out checklist covering Vt coverage, extraction files, capacitor options, hard IP and I/O domains.

September 26, 2026Updated September 26, 20269 min readBy Henry

Case StudyTape-OutASICFoundryProcess Node

This is a real preparation, not a composite. The program targets SMIC 40 nm Low Leakage at 1.1 V and 2.5 V, and the three gaps below were raised with the foundry before layout closed. Names and figures that belong to the customer are withheld; the technical content is reported as it stands.

Most tape-out delays that look like design problems are delivery problems. The design was fine; the library, the extraction techfile or the capacitor option the circuit assumed was never in the package that got handed over.

The library set in use

The program is running on SMIC 40LL, a 1.1 V / 2.5 V low-leakage logic process. The delivered kit contains a standard cell library in three threshold-voltage flavours — low, standard and high Vt — released in October 2024; a 3.3 V I/O cell library on a much older release, which is normal; a Cadence OA-format PDK; and a PLL hard macro.

That is a normal-looking kit. It is also the shape of kit that hides the three problems below.

Gap 1: no parasitic extraction techfile

The delivered standard cell library does not include the matching QRC technology file. Without it, post-layout extraction cannot run, which means every post-layout timing, power and noise number is provisional.

This is the most common of the three and the cheapest to close, because the fix is a request rather than a design change. The risk is sequencing: place-and-route can proceed happily without the file, so the absence surfaces only when the first extraction run fails — by which point layout decisions have been frozen against an estimate.

Extraction techfiles are frequently delivered separately from the standard cell library rather than inside it. Checking that the file exists and matches the library version is a five-minute task in week one.

Gap 2: MOM capacitors only, MIM marked optional

The delivered PDK contains MOM capacitors only. The documentation states MIM capacitors are optional for the process, and the program needs them.

The two are not interchangeable. MOM capacitors are formed from the interconnect stack itself, so they cost no extra process layer but have lower capacitance density and worse matching. MIM uses a dedicated dielectric layer with far better density and matching. Any design carrying precision RC, a PLL loop filter, a reference or a data converter needs to know which one it is getting, because the answer changes the area and the achievable accuracy.

If MIM is optional and the circuit requires it, that is a request to make at kit release time. Receiving a MIM-enabled kit revision after layout has started means re-doing the affected blocks.

Gap 3: hard IP terms for an NTO run

The third question was commercial rather than technical: what does the node's PLL cost when the wafer is run as a dedicated NTO rather than as a shared shuttle? The two can be quoted differently, and the answer affects whether the macro is used at all.

The same check applies to any foundry-supplied memory compiler output: compiler version, node support, and whether the generated instances are covered by the delivered extraction and verification decks.

The checklist this program produced

Every item below is answerable in an email before layout starts. Getting the answers in writing matters more than getting them quickly, because a verbal confirmation of a file that later turns out to be absent is worth nothing at the point where it costs a tape-out slot.

Full list of delivered libraries with version and release date, per type
Confirmation that extraction techfiles matching those versions are included
Confirmation of whether MIM capacitors are enabled in the delivered PDK revision
Availability and commercial basis for each hard macro when the run is NTO rather than shared
Pad library voltage domains, ESD levels and version against the core library
What the turnaround is if any of the above has to be re-released

Outcome

The three gaps were identified and raised before layout closed, which is the whole point of the check — finding them while they are a request rather than a re-spin. Each one was closed against the programme's requirements, and the kit delivered met what the design needed.

Article FAQ

Quick answers tied to this topic

Not universally, but it is better on the two parameters that usually matter: density and matching. MIM uses a dedicated dielectric layer, so it gives far more capacitance per unit area and far tighter matching between nominally identical devices. MOM is built from the routing stack, so it costs no extra process layer but consumes more area for the same value and matches worse. If your capacitor only needs to be approximately right — a decoupling cap, a coarse filter — MOM is fine. If it sets a time constant, a loop bandwidth or a converter accuracy, ask for MIM.

You can place and route, but you cannot sign off. Every post-layout timing, power and noise number depends on extraction, and without the matching techfile those numbers are provisional at best. The practical risk is that layout decisions get frozen against an estimate, and re-work is required once real extraction arrives. If a techfile has to be requested, request it before floorplan closes.

The technical checks are identical — the kit contents do not depend on how the wafer is paid for. What differs is the commercial side: hard IP terms, and how quickly a missing file can be re-released when you are one participant on a shared run rather than the owner of the mask set. On a shared run you are working to someone else's calendar, which makes front-loading these checks more important, not less.

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